baseband/acc100: add info get function
Add in the "info_get" function to the driver, to allow us to query the device. No processing capability are available yet. Linking bbdev-test to support the PMD with null capability. Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
This commit is contained in:
parent
4cf9007979
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9200ffa5cd
@ -12,3 +12,6 @@ endif
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if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC')
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deps += ['pmd_bbdev_fpga_5gnr_fec']
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endif
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if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_ACC100')
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deps += ['pmd_bbdev_acc100']
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endif
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96
drivers/baseband/acc100/rte_acc100_cfg.h
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96
drivers/baseband/acc100/rte_acc100_cfg.h
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@ -0,0 +1,96 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2020 Intel Corporation
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*/
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#ifndef _RTE_ACC100_CFG_H_
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#define _RTE_ACC100_CFG_H_
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/**
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* @file rte_acc100_cfg.h
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*
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* Functions for configuring ACC100 HW, exposed directly to applications.
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* Configuration related to encoding/decoding is done through the
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* librte_bbdev library.
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*
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* @warning
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* @b EXPERIMENTAL: this API may change without prior notice
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**< Number of Virtual Functions ACC100 supports */
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#define RTE_ACC100_NUM_VFS 16
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/**
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* Definition of Queue Topology for ACC100 Configuration
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* Some level of details is abstracted out to expose a clean interface
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* given that comprehensive flexibility is not required
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*/
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struct rte_acc100_queue_topology {
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/** Number of QGroups in incremental order of priority */
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uint16_t num_qgroups;
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/**
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* All QGroups have the same number of AQs here.
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* Note : Could be made a 16-array if more flexibility is really
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* required
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*/
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uint16_t num_aqs_per_groups;
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/**
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* Depth of the AQs is the same of all QGroups here. Log2 Enum : 2^N
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* Note : Could be made a 16-array if more flexibility is really
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* required
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*/
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uint16_t aq_depth_log2;
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/**
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* Index of the first Queue Group Index - assuming contiguity
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* Initialized as -1
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*/
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int8_t first_qgroup_index;
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};
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/**
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* Definition of Arbitration related parameters for ACC100 Configuration
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*/
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struct rte_acc100_arbitration {
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/** Default Weight for VF Fairness Arbitration */
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uint16_t round_robin_weight;
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uint32_t gbr_threshold1; /**< Guaranteed Bitrate Threshold 1 */
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uint32_t gbr_threshold2; /**< Guaranteed Bitrate Threshold 2 */
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};
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/**
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* Structure to pass ACC100 configuration.
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* Note: all VF Bundles will have the same configuration.
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*/
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struct rte_acc100_conf {
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bool pf_mode_en; /**< 1 if PF is used for dataplane, 0 for VFs */
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/** 1 if input '1' bit is represented by a positive LLR value, 0 if '1'
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* bit is represented by a negative value.
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*/
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bool input_pos_llr_1_bit;
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/** 1 if output '1' bit is represented by a positive value, 0 if '1'
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* bit is represented by a negative value.
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*/
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bool output_pos_llr_1_bit;
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uint16_t num_vf_bundles; /**< Number of VF bundles to setup */
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/** Queue topology for each operation type */
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struct rte_acc100_queue_topology q_ul_4g;
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struct rte_acc100_queue_topology q_dl_4g;
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struct rte_acc100_queue_topology q_ul_5g;
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struct rte_acc100_queue_topology q_dl_5g;
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/** Arbitration configuration for each operation type */
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struct rte_acc100_arbitration arb_ul_4g[RTE_ACC100_NUM_VFS];
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struct rte_acc100_arbitration arb_dl_4g[RTE_ACC100_NUM_VFS];
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struct rte_acc100_arbitration arb_ul_5g[RTE_ACC100_NUM_VFS];
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struct rte_acc100_arbitration arb_dl_5g[RTE_ACC100_NUM_VFS];
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTE_ACC100_CFG_H_ */
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@ -26,6 +26,188 @@ RTE_LOG_REGISTER(acc100_logtype, pmd.bb.acc100, DEBUG);
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RTE_LOG_REGISTER(acc100_logtype, pmd.bb.acc100, NOTICE);
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#endif
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/* Read a register of a ACC100 device */
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static inline uint32_t
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acc100_reg_read(struct acc100_device *d, uint32_t offset)
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{
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void *reg_addr = RTE_PTR_ADD(d->mmio_base, offset);
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uint32_t ret = *((volatile uint32_t *)(reg_addr));
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return rte_le_to_cpu_32(ret);
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}
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/* Calculate the offset of the enqueue register */
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static inline uint32_t
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queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id)
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{
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if (pf_device)
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return ((vf_id << 12) + (qgrp_id << 7) + (aq_id << 3) +
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HWPfQmgrIngressAq);
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else
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return ((qgrp_id << 7) + (aq_id << 3) +
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HWVfQmgrIngressAq);
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}
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enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, NUM_ACC};
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/* Return the queue topology for a Queue Group Index */
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static inline void
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qtopFromAcc(struct rte_acc100_queue_topology **qtop, int acc_enum,
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struct rte_acc100_conf *acc100_conf)
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{
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struct rte_acc100_queue_topology *p_qtop;
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p_qtop = NULL;
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switch (acc_enum) {
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case UL_4G:
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p_qtop = &(acc100_conf->q_ul_4g);
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break;
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case UL_5G:
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p_qtop = &(acc100_conf->q_ul_5g);
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break;
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case DL_4G:
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p_qtop = &(acc100_conf->q_dl_4g);
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break;
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case DL_5G:
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p_qtop = &(acc100_conf->q_dl_5g);
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break;
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default:
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/* NOTREACHED */
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rte_bbdev_log(ERR, "Unexpected error evaluating qtopFromAcc");
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break;
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}
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*qtop = p_qtop;
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}
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static void
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initQTop(struct rte_acc100_conf *acc100_conf)
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{
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acc100_conf->q_ul_4g.num_aqs_per_groups = 0;
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acc100_conf->q_ul_4g.num_qgroups = 0;
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acc100_conf->q_ul_4g.first_qgroup_index = -1;
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acc100_conf->q_ul_5g.num_aqs_per_groups = 0;
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acc100_conf->q_ul_5g.num_qgroups = 0;
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acc100_conf->q_ul_5g.first_qgroup_index = -1;
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acc100_conf->q_dl_4g.num_aqs_per_groups = 0;
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acc100_conf->q_dl_4g.num_qgroups = 0;
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acc100_conf->q_dl_4g.first_qgroup_index = -1;
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acc100_conf->q_dl_5g.num_aqs_per_groups = 0;
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acc100_conf->q_dl_5g.num_qgroups = 0;
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acc100_conf->q_dl_5g.first_qgroup_index = -1;
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}
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static inline void
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updateQtop(uint8_t acc, uint8_t qg, struct rte_acc100_conf *acc100_conf,
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struct acc100_device *d) {
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uint32_t reg;
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struct rte_acc100_queue_topology *q_top = NULL;
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qtopFromAcc(&q_top, acc, acc100_conf);
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if (unlikely(q_top == NULL))
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return;
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uint16_t aq;
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q_top->num_qgroups++;
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if (q_top->first_qgroup_index == -1) {
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q_top->first_qgroup_index = qg;
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/* Can be optimized to assume all are enabled by default */
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reg = acc100_reg_read(d, queue_offset(d->pf_device,
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0, qg, ACC100_NUM_AQS - 1));
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if (reg & ACC100_QUEUE_ENABLE) {
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q_top->num_aqs_per_groups = ACC100_NUM_AQS;
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return;
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}
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q_top->num_aqs_per_groups = 0;
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for (aq = 0; aq < ACC100_NUM_AQS; aq++) {
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reg = acc100_reg_read(d, queue_offset(d->pf_device,
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0, qg, aq));
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if (reg & ACC100_QUEUE_ENABLE)
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q_top->num_aqs_per_groups++;
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}
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}
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}
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/* Fetch configuration enabled for the PF/VF using MMIO Read (slow) */
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static inline void
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fetch_acc100_config(struct rte_bbdev *dev)
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{
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struct acc100_device *d = dev->data->dev_private;
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struct rte_acc100_conf *acc100_conf = &d->acc100_conf;
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const struct acc100_registry_addr *reg_addr;
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uint8_t acc, qg;
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uint32_t reg, reg_aq, reg_len0, reg_len1;
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uint32_t reg_mode;
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/* No need to retrieve the configuration is already done */
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if (d->configured)
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return;
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/* Choose correct registry addresses for the device type */
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if (d->pf_device)
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reg_addr = &pf_reg_addr;
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else
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reg_addr = &vf_reg_addr;
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d->ddr_size = (1 + acc100_reg_read(d, reg_addr->ddr_range)) << 10;
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/* Single VF Bundle by VF */
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acc100_conf->num_vf_bundles = 1;
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initQTop(acc100_conf);
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struct rte_acc100_queue_topology *q_top = NULL;
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int qman_func_id[ACC100_NUM_ACCS] = {ACC100_ACCMAP_0, ACC100_ACCMAP_1,
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ACC100_ACCMAP_2, ACC100_ACCMAP_3, ACC100_ACCMAP_4};
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reg = acc100_reg_read(d, reg_addr->qman_group_func);
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for (qg = 0; qg < ACC100_NUM_QGRPS_PER_WORD; qg++) {
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reg_aq = acc100_reg_read(d,
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queue_offset(d->pf_device, 0, qg, 0));
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if (reg_aq & ACC100_QUEUE_ENABLE) {
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uint32_t idx = (reg >> (qg * 4)) & 0x7;
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if (idx < ACC100_NUM_ACCS) {
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acc = qman_func_id[idx];
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updateQtop(acc, qg, acc100_conf, d);
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}
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}
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}
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/* Check the depth of the AQs*/
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reg_len0 = acc100_reg_read(d, reg_addr->depth_log0_offset);
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reg_len1 = acc100_reg_read(d, reg_addr->depth_log1_offset);
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for (acc = 0; acc < NUM_ACC; acc++) {
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qtopFromAcc(&q_top, acc, acc100_conf);
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if (q_top->first_qgroup_index < ACC100_NUM_QGRPS_PER_WORD)
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q_top->aq_depth_log2 = (reg_len0 >>
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(q_top->first_qgroup_index * 4))
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& 0xF;
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else
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q_top->aq_depth_log2 = (reg_len1 >>
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((q_top->first_qgroup_index -
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ACC100_NUM_QGRPS_PER_WORD) * 4))
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& 0xF;
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}
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/* Read PF mode */
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if (d->pf_device) {
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reg_mode = acc100_reg_read(d, HWPfHiPfMode);
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acc100_conf->pf_mode_en = (reg_mode == ACC100_PF_VAL) ? 1 : 0;
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}
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rte_bbdev_log_debug(
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"%s Config LLR SIGN IN/OUT %s %s QG %u %u %u %u AQ %u %u %u %u Len %u %u %u %u\n",
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(d->pf_device) ? "PF" : "VF",
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(acc100_conf->input_pos_llr_1_bit) ? "POS" : "NEG",
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(acc100_conf->output_pos_llr_1_bit) ? "POS" : "NEG",
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acc100_conf->q_ul_4g.num_qgroups,
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acc100_conf->q_dl_4g.num_qgroups,
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acc100_conf->q_ul_5g.num_qgroups,
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acc100_conf->q_dl_5g.num_qgroups,
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acc100_conf->q_ul_4g.num_aqs_per_groups,
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acc100_conf->q_dl_4g.num_aqs_per_groups,
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acc100_conf->q_ul_5g.num_aqs_per_groups,
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acc100_conf->q_dl_5g.num_aqs_per_groups,
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acc100_conf->q_ul_4g.aq_depth_log2,
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acc100_conf->q_dl_4g.aq_depth_log2,
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acc100_conf->q_ul_5g.aq_depth_log2,
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acc100_conf->q_dl_5g.aq_depth_log2);
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}
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/* Free 64MB memory used for software rings */
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static int
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acc100_dev_close(struct rte_bbdev *dev __rte_unused)
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@ -33,8 +215,55 @@ acc100_dev_close(struct rte_bbdev *dev __rte_unused)
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return 0;
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}
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/* Get ACC100 device info */
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static void
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acc100_dev_info_get(struct rte_bbdev *dev,
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struct rte_bbdev_driver_info *dev_info)
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{
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struct acc100_device *d = dev->data->dev_private;
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static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
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RTE_BBDEV_END_OF_CAPABILITIES_LIST()
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};
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static struct rte_bbdev_queue_conf default_queue_conf;
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default_queue_conf.socket = dev->data->socket_id;
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default_queue_conf.queue_size = ACC100_MAX_QUEUE_DEPTH;
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dev_info->driver_name = dev->device->driver->name;
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/* Read and save the populated config from ACC100 registers */
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fetch_acc100_config(dev);
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/* This isn't ideal because it reports the maximum number of queues but
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* does not provide info on how many can be uplink/downlink or different
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* priorities
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*/
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dev_info->max_num_queues =
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d->acc100_conf.q_dl_5g.num_aqs_per_groups *
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d->acc100_conf.q_dl_5g.num_qgroups +
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d->acc100_conf.q_ul_5g.num_aqs_per_groups *
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d->acc100_conf.q_ul_5g.num_qgroups +
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d->acc100_conf.q_dl_4g.num_aqs_per_groups *
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d->acc100_conf.q_dl_4g.num_qgroups +
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d->acc100_conf.q_ul_4g.num_aqs_per_groups *
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d->acc100_conf.q_ul_4g.num_qgroups;
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dev_info->queue_size_lim = ACC100_MAX_QUEUE_DEPTH;
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dev_info->hardware_accelerated = true;
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dev_info->max_dl_queue_priority =
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d->acc100_conf.q_dl_4g.num_qgroups - 1;
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dev_info->max_ul_queue_priority =
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d->acc100_conf.q_ul_4g.num_qgroups - 1;
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dev_info->default_queue_conf = default_queue_conf;
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dev_info->cpu_flag_reqs = NULL;
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dev_info->min_alignment = 64;
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dev_info->capabilities = bbdev_capabilities;
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dev_info->harq_buffer_size = d->ddr_size;
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}
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static const struct rte_bbdev_ops acc100_bbdev_ops = {
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.close = acc100_dev_close,
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.info_get = acc100_dev_info_get,
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};
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/* ACC100 PCI PF address map */
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@ -7,6 +7,7 @@
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#include "acc100_pf_enum.h"
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#include "acc100_vf_enum.h"
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#include "rte_acc100_cfg.h"
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/* Helper macro for logging */
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#define rte_bbdev_log(level, fmt, ...) \
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@ -98,6 +99,13 @@
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#define ACC100_SIG_UL_4G_LAST 21
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#define ACC100_SIG_DL_4G 27
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#define ACC100_SIG_DL_4G_LAST 31
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#define ACC100_NUM_ACCS 5
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#define ACC100_ACCMAP_0 0
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#define ACC100_ACCMAP_1 2
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#define ACC100_ACCMAP_2 1
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#define ACC100_ACCMAP_3 3
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#define ACC100_ACCMAP_4 4
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#define ACC100_PF_VAL 2
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/* max number of iterations to allocate memory block for all rings */
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#define ACC100_SW_RING_MEM_ALLOC_ATTEMPTS 5
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@ -517,6 +525,8 @@ static const struct acc100_registry_addr vf_reg_addr = {
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/* Private data structure for each ACC100 device */
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struct acc100_device {
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void *mmio_base; /**< Base address of MMIO registers (BAR0) */
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uint32_t ddr_size; /* Size in kB */
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struct rte_acc100_conf acc100_conf; /* ACC100 Initial configuration */
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bool pf_device; /**< True if this is a PF ACC100 device */
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bool configured; /**< True if this ACC100 device is configured */
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};
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