net/octeontx2: add device start operation
Add device start operation and update the correct function pointers for Rx and Tx burst functions. This patch also update the octeontx2 NIC specific documentation. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Nithin Dabilpuram
Ferruh Yigit
parent
ddc1bc26e9
commit
920717e4d8
@ -34,6 +34,7 @@ Features of the OCTEON TX2 Ethdev PMD are:
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- Vector Poll mode driver
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- Debug utilities - Context dump and error interrupt support
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- IEEE1588 timestamping
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- HW offloaded `ethdev Rx queue` to `eventdev event queue` packet injection
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Prerequisites
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-------------
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@ -49,6 +50,63 @@ The following options may be modified in the ``config`` file.
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Toggle compilation of the ``librte_pmd_octeontx2`` driver.
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Driver compilation and testing
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------------------------------
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Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
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for details.
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To compile the OCTEON TX2 PMD for Linux arm64 gcc,
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use arm64-octeontx2-linux-gcc as target.
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#. Running testpmd:
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Follow instructions available in the document
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:ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
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to run testpmd.
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Example output:
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.. code-block:: console
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./build/app/testpmd -c 0x300 -w 0002:02:00.0 -- --portmask=0x1 --nb-cores=1 --port-topology=loop --rxq=1 --txq=1
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EAL: Detected 24 lcore(s)
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EAL: Detected 1 NUMA nodes
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EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
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EAL: No available hugepages reported in hugepages-2048kB
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EAL: Probing VFIO support...
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EAL: VFIO support initialized
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EAL: PCI device 0002:02:00.0 on NUMA socket 0
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EAL: probe driver: 177d:a063 net_octeontx2
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EAL: using IOMMU type 1 (Type 1)
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testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=267456, size=2176, socket=0
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testpmd: preferred mempool ops selected: octeontx2_npa
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Configuring Port 0 (socket 0)
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PMD: Port 0: Link Up - speed 40000 Mbps - full-duplex
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Port 0: link state change event
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Port 0: 36:10:66:88:7A:57
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Checking link statuses...
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Done
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No commandline core given, start packet forwarding
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io packet forwarding - ports=1 - cores=1 - streams=1 - NUMA support enabled, MP allocation mode: native
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Logical Core 9 (socket 0) forwards packets on 1 streams:
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RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
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io packet forwarding packets/burst=32
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nb forwarding cores=1 - nb forwarding ports=1
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port 0: RX queue number: 1 Tx queue number: 1
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Rx offloads=0x0 Tx offloads=0x10000
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RX queue: 0
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RX desc=512 - RX free threshold=0
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RX threshold registers: pthresh=0 hthresh=0 wthresh=0
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RX Offloads=0x0
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TX queue: 0
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TX desc=512 - TX free threshold=0
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TX threshold registers: pthresh=0 hthresh=0 wthresh=0
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TX offloads=0x10000 - TX RS bit threshold=0
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Press enter to exit
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Runtime Config Options
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----------------------
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@ -116,6 +174,39 @@ Runtime Config Options
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parameters to all the PCIe devices if application requires to configure on
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all the ethdev ports.
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Limitations
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-----------
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``mempool_octeontx2`` external mempool handler dependency
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The OCTEON TX2 SoC family NIC has inbuilt HW assisted external mempool manager.
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``net_octeontx2`` pmd only works with ``mempool_octeontx2`` mempool handler
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as it is performance wise most effective way for packet allocation and Tx buffer
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recycling on OCTEON TX2 SoC platform.
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CRC striping
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~~~~~~~~~~~~
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The OCTEON TX2 SoC family NICs strip the CRC for every packet being received by
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the host interface irrespective of the offload configuration.
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Debugging Options
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-----------------
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.. _table_octeontx2_ethdev_debug_options:
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.. table:: OCTEON TX2 ethdev debug options
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+---+------------+-------------------------------------------------------+
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| # | Component | EAL log command |
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+===+============+=======================================================+
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| 1 | NIX | --log-level='pmd\.net.octeontx2,8' |
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+---+------------+-------------------------------------------------------+
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| 2 | NPC | --log-level='pmd\.net.octeontx2\.flow,8' |
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+---+------------+-------------------------------------------------------+
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RTE Flow Support
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----------------
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@ -135,6 +135,55 @@ otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
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return otx2_mbox_process(mbox);
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}
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static int
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npc_rx_enable(struct otx2_eth_dev *dev)
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{
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struct otx2_mbox *mbox = dev->mbox;
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otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
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return otx2_mbox_process(mbox);
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}
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static int
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npc_rx_disable(struct otx2_eth_dev *dev)
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{
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struct otx2_mbox *mbox = dev->mbox;
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otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
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return otx2_mbox_process(mbox);
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}
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static int
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nix_cgx_start_link_event(struct otx2_eth_dev *dev)
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{
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struct otx2_mbox *mbox = dev->mbox;
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if (otx2_dev_is_vf(dev))
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return 0;
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otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
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return otx2_mbox_process(mbox);
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}
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static int
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cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
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{
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struct otx2_mbox *mbox = dev->mbox;
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if (otx2_dev_is_vf(dev))
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return 0;
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if (en)
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otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
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else
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otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
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return otx2_mbox_process(mbox);
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}
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static inline void
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nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
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{
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@ -478,6 +527,74 @@ nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
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return NIX_MAXSQESZ_W8;
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}
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static uint16_t
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nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct rte_eth_dev_data *data = eth_dev->data;
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struct rte_eth_conf *conf = &data->dev_conf;
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struct rte_eth_rxmode *rxmode = &conf->rxmode;
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uint16_t flags = 0;
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if (rxmode->mq_mode == ETH_MQ_RX_RSS)
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flags |= NIX_RX_OFFLOAD_RSS_F;
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if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
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DEV_RX_OFFLOAD_UDP_CKSUM))
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flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
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if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
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DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
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flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
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if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
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flags |= NIX_RX_MULTI_SEG_F;
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if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
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DEV_RX_OFFLOAD_QINQ_STRIP))
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flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
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if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
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flags |= NIX_RX_OFFLOAD_TSTAMP_F;
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return flags;
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}
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static uint16_t
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nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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uint64_t conf = dev->tx_offloads;
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uint16_t flags = 0;
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/* Fastpath is dependent on these enums */
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RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
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RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
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RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
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if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
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conf & DEV_TX_OFFLOAD_QINQ_INSERT)
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flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
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if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
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conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
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flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
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if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
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conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
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conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
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conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
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flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
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if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
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flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
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if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
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flags |= NIX_TX_MULTI_SEG_F;
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return flags;
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}
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static int
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nix_sq_init(struct otx2_eth_txq *txq)
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{
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@ -1111,6 +1228,8 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
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dev->rx_offloads = rxmode->offloads;
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dev->tx_offloads = txmode->offloads;
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dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
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dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
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dev->rss_info.rss_grps = NIX_RSS_GRPS;
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nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
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@ -1150,6 +1269,13 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
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goto free_nix_lf;
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}
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/* Configure loop back mode */
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rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
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if (rc) {
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otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
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goto free_nix_lf;
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}
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rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
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if (rc) {
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otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
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@ -1299,6 +1425,59 @@ otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
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return rc;
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}
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static int
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otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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int rc, i;
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/* Start rx queues */
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for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
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rc = otx2_nix_rx_queue_start(eth_dev, i);
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if (rc)
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return rc;
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}
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/* Start tx queues */
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for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
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rc = otx2_nix_tx_queue_start(eth_dev, i);
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if (rc)
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return rc;
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}
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rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
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if (rc) {
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otx2_err("Failed to update flow ctrl mode %d", rc);
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return rc;
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}
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rc = npc_rx_enable(dev);
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if (rc) {
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otx2_err("Failed to enable NPC rx %d", rc);
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return rc;
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}
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otx2_nix_toggle_flag_link_cfg(dev, true);
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rc = nix_cgx_start_link_event(dev);
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if (rc) {
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otx2_err("Failed to start cgx link event %d", rc);
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goto rx_disable;
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}
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otx2_nix_toggle_flag_link_cfg(dev, false);
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otx2_eth_set_tx_function(eth_dev);
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otx2_eth_set_rx_function(eth_dev);
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return 0;
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rx_disable:
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npc_rx_disable(dev);
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otx2_nix_toggle_flag_link_cfg(dev, false);
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return rc;
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}
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/* Initialize and register driver with DPDK Application */
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static const struct eth_dev_ops otx2_eth_dev_ops = {
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.dev_infos_get = otx2_nix_info_get,
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@ -1308,6 +1487,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
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.tx_queue_release = otx2_nix_tx_queue_release,
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.rx_queue_setup = otx2_nix_rx_queue_setup,
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.rx_queue_release = otx2_nix_rx_queue_release,
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.dev_start = otx2_nix_dev_start,
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.tx_queue_start = otx2_nix_tx_queue_start,
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.tx_queue_stop = otx2_nix_tx_queue_stop,
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.rx_queue_start = otx2_nix_rx_queue_start,
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@ -528,8 +528,10 @@ otx2_flow_destroy(struct rte_eth_dev *dev,
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return -EINVAL;
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/* Clear mark offload flag if there are no more mark actions */
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if (rte_atomic32_sub_return(&npc->mark_actions, 1) == 0)
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if (rte_atomic32_sub_return(&npc->mark_actions, 1) == 0) {
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hw->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
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otx2_eth_set_rx_function(dev);
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}
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}
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rc = flow_free_rss_action(dev, flow);
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@ -938,9 +938,11 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev,
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if (mark)
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flow->npc_action |= (uint64_t)mark << 40;
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if (rte_atomic32_read(&npc->mark_actions) == 1)
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if (rte_atomic32_read(&npc->mark_actions) == 1) {
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hw->rx_offload_flags |=
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NIX_RX_OFFLOAD_MARK_UPDATE_F;
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otx2_eth_set_rx_function(dev);
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}
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set_pf_func:
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/* Ideally AF must ensure that correct pf_func is set */
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@ -118,6 +118,10 @@ otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
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struct otx2_eth_txq *txq = eth_dev->data->tx_queues[i];
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otx2_nix_form_default_desc(txq);
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}
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/* Setting up the function pointers as per new offload flags */
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otx2_eth_set_rx_function(eth_dev);
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otx2_eth_set_tx_function(eth_dev);
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}
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return rc;
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}
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@ -147,6 +151,10 @@ otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev)
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struct otx2_eth_txq *txq = eth_dev->data->tx_queues[i];
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otx2_nix_form_default_desc(txq);
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}
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/* Setting up the function pointers as per new offload flags */
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otx2_eth_set_rx_function(eth_dev);
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otx2_eth_set_tx_function(eth_dev);
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}
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return rc;
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}
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@ -760,6 +760,7 @@ otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
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DEV_RX_OFFLOAD_QINQ_STRIP)) {
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dev->rx_offloads |= offloads;
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dev->rx_offload_flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
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otx2_eth_set_rx_function(eth_dev);
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}
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done:
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