igb: RSS RETA configuration
Signed-off-by: Intel
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01a638e15d
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@ -119,6 +119,10 @@ static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
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uint16_t vlan_id, int on);
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uint16_t vlan_id, int on);
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static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
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static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
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static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
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static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
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static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
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struct rte_eth_rss_reta *reta_conf);
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static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
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struct rte_eth_rss_reta *reta_conf);
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/*
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/*
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* Define VF Stats MACRO for Non "cleared on read" register
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* Define VF Stats MACRO for Non "cleared on read" register
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@ -184,6 +188,8 @@ static struct eth_dev_ops eth_igb_ops = {
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.flow_ctrl_set = eth_igb_flow_ctrl_set,
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.flow_ctrl_set = eth_igb_flow_ctrl_set,
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.mac_addr_add = eth_igb_rar_set,
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.mac_addr_add = eth_igb_rar_set,
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.mac_addr_remove = eth_igb_rar_clear,
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.mac_addr_remove = eth_igb_rar_clear,
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.reta_update = eth_igb_rss_reta_update,
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.reta_query = eth_igb_rss_reta_query,
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};
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};
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/*
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/*
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@ -1895,3 +1901,74 @@ igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
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return 0;
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return 0;
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}
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}
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static int
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eth_igb_rss_reta_update(struct rte_eth_dev *dev,
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struct rte_eth_rss_reta *reta_conf)
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{
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uint8_t i,j,mask;
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uint32_t reta;
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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/*
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* Update Redirection Table RETA[n],n=0...31,The redirection table has
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* 128-entries in 32 registers
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*/
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for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
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if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
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mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
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else
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mask = (uint8_t)((reta_conf->mask_hi >>
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(i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
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if (mask != 0) {
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reta = 0;
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/* If all 4 entries were set,don't need read RETA register */
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if (mask != 0xF)
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reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
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for (j = 0; j < 4; j++) {
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if (mask & (0x1 << j)) {
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if (mask != 0xF)
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reta &= ~(0xFF << 8 * j);
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reta |= reta_conf->reta[i + j] << 8 * j;
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}
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}
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E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
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}
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}
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return 0;
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}
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static int
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eth_igb_rss_reta_query(struct rte_eth_dev *dev,
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struct rte_eth_rss_reta *reta_conf)
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{
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uint8_t i,j,mask;
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uint32_t reta;
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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/*
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* Read Redirection Table RETA[n],n=0...31,The redirection table has
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* 128-entries in 32 registers
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*/
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for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
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if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
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mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
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else
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mask = (uint8_t)((reta_conf->mask_hi >>
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(i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
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if (mask != 0) {
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reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
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for (j = 0; j < 4; j++) {
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if (mask & (0x1 << j))
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reta_conf->reta[i + j] =
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(uint8_t)((reta >> 8 * j) & 0xFF);
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}
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}
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}
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return 0;
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}
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