net/ice: add queue start and stop for DCF
Add queue start and stop in DCF. Support queue enable and disable through virtual channel. Add support for Rx queue mbufs allocation and queue reset. Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Signed-off-by: Ting Xu <ting.xu@intel.com> Reviewed-by: Qiming Yang <qiming.yang@intel.com>
This commit is contained in:
Qi Zhang
Ferruh Yigit
parent
4b0d391f0e
commit
929eceefab
@ -936,3 +936,60 @@ ice_dcf_config_irq_map(struct ice_dcf_hw *hw)
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rte_free(map_info);
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return err;
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}
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int
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ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on)
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{
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struct virtchnl_queue_select queue_select;
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struct dcf_virtchnl_cmd args;
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int err;
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memset(&queue_select, 0, sizeof(queue_select));
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queue_select.vsi_id = hw->vsi_res->vsi_id;
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if (rx)
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queue_select.rx_queues |= 1 << qid;
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else
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queue_select.tx_queues |= 1 << qid;
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memset(&args, 0, sizeof(args));
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if (on)
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args.v_op = VIRTCHNL_OP_ENABLE_QUEUES;
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else
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args.v_op = VIRTCHNL_OP_DISABLE_QUEUES;
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args.req_msg = (u8 *)&queue_select;
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args.req_msglen = sizeof(queue_select);
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err = ice_dcf_execute_virtchnl_cmd(hw, &args);
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if (err)
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PMD_DRV_LOG(ERR, "Failed to execute command of %s",
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on ? "OP_ENABLE_QUEUES" : "OP_DISABLE_QUEUES");
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return err;
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}
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int
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ice_dcf_disable_queues(struct ice_dcf_hw *hw)
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{
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struct virtchnl_queue_select queue_select;
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struct dcf_virtchnl_cmd args;
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int err;
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memset(&queue_select, 0, sizeof(queue_select));
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queue_select.vsi_id = hw->vsi_res->vsi_id;
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queue_select.rx_queues = BIT(hw->eth_dev->data->nb_rx_queues) - 1;
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queue_select.tx_queues = BIT(hw->eth_dev->data->nb_tx_queues) - 1;
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memset(&args, 0, sizeof(args));
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args.v_op = VIRTCHNL_OP_DISABLE_QUEUES;
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args.req_msg = (u8 *)&queue_select;
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args.req_msglen = sizeof(queue_select);
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err = ice_dcf_execute_virtchnl_cmd(hw, &args);
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if (err)
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PMD_DRV_LOG(ERR,
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"Failed to execute command of OP_DISABLE_QUEUES");
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return err;
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}
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@ -70,5 +70,6 @@ void ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw);
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int ice_dcf_init_rss(struct ice_dcf_hw *hw);
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int ice_dcf_configure_queues(struct ice_dcf_hw *hw);
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int ice_dcf_config_irq_map(struct ice_dcf_hw *hw);
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int ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on);
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int ice_dcf_disable_queues(struct ice_dcf_hw *hw);
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#endif /* _ICE_DCF_H_ */
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@ -227,6 +227,272 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,
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return 0;
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}
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static int
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alloc_rxq_mbufs(struct ice_rx_queue *rxq)
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{
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volatile union ice_32b_rx_flex_desc *rxd;
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struct rte_mbuf *mbuf = NULL;
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uint64_t dma_addr;
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uint16_t i;
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for (i = 0; i < rxq->nb_rx_desc; i++) {
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mbuf = rte_mbuf_raw_alloc(rxq->mp);
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if (unlikely(!mbuf)) {
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PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
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return -ENOMEM;
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}
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rte_mbuf_refcnt_set(mbuf, 1);
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mbuf->next = NULL;
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mbuf->data_off = RTE_PKTMBUF_HEADROOM;
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mbuf->nb_segs = 1;
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mbuf->port = rxq->port_id;
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dma_addr =
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rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
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rxd = &rxq->rx_ring[i];
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rxd->read.pkt_addr = dma_addr;
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rxd->read.hdr_addr = 0;
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rxd->read.rsvd1 = 0;
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rxd->read.rsvd2 = 0;
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rxq->sw_ring[i].mbuf = (void *)mbuf;
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}
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return 0;
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}
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static int
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ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
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{
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struct ice_dcf_adapter *ad = dev->data->dev_private;
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struct iavf_hw *hw = &ad->real_hw.avf;
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struct ice_rx_queue *rxq;
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int err = 0;
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if (rx_queue_id >= dev->data->nb_rx_queues)
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return -EINVAL;
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rxq = dev->data->rx_queues[rx_queue_id];
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err = alloc_rxq_mbufs(rxq);
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if (err) {
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PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
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return err;
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}
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rte_wmb();
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/* Init the RX tail register. */
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IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
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IAVF_WRITE_FLUSH(hw);
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/* Ready to switch the queue on */
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err = ice_dcf_switch_queue(&ad->real_hw, rx_queue_id, true, true);
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if (err) {
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PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
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rx_queue_id);
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return err;
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}
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dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
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return 0;
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}
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static inline void
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reset_rx_queue(struct ice_rx_queue *rxq)
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{
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uint16_t len;
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uint32_t i;
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if (!rxq)
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return;
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len = rxq->nb_rx_desc + ICE_RX_MAX_BURST;
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for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
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((volatile char *)rxq->rx_ring)[i] = 0;
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memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
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for (i = 0; i < ICE_RX_MAX_BURST; i++)
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rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
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/* for rx bulk */
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rxq->rx_nb_avail = 0;
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rxq->rx_next_avail = 0;
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rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
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rxq->rx_tail = 0;
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rxq->nb_rx_hold = 0;
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rxq->pkt_first_seg = NULL;
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rxq->pkt_last_seg = NULL;
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}
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static inline void
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reset_tx_queue(struct ice_tx_queue *txq)
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{
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struct ice_tx_entry *txe;
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uint32_t i, size;
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uint16_t prev;
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if (!txq) {
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PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
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return;
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}
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txe = txq->sw_ring;
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size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
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for (i = 0; i < size; i++)
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((volatile char *)txq->tx_ring)[i] = 0;
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prev = (uint16_t)(txq->nb_tx_desc - 1);
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for (i = 0; i < txq->nb_tx_desc; i++) {
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txq->tx_ring[i].cmd_type_offset_bsz =
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rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
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txe[i].mbuf = NULL;
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txe[i].last_id = i;
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txe[prev].next_id = i;
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prev = i;
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}
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txq->tx_tail = 0;
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txq->nb_tx_used = 0;
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txq->last_desc_cleaned = txq->nb_tx_desc - 1;
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txq->nb_tx_free = txq->nb_tx_desc - 1;
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txq->tx_next_dd = txq->tx_rs_thresh - 1;
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txq->tx_next_rs = txq->tx_rs_thresh - 1;
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}
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static int
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ice_dcf_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
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{
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struct ice_dcf_adapter *ad = dev->data->dev_private;
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struct ice_dcf_hw *hw = &ad->real_hw;
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struct ice_rx_queue *rxq;
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int err;
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if (rx_queue_id >= dev->data->nb_rx_queues)
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return -EINVAL;
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err = ice_dcf_switch_queue(hw, rx_queue_id, true, false);
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if (err) {
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PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
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rx_queue_id);
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return err;
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}
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rxq = dev->data->rx_queues[rx_queue_id];
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rxq->rx_rel_mbufs(rxq);
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reset_rx_queue(rxq);
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dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
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return 0;
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}
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static int
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ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
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{
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struct ice_dcf_adapter *ad = dev->data->dev_private;
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struct iavf_hw *hw = &ad->real_hw.avf;
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struct ice_tx_queue *txq;
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int err = 0;
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if (tx_queue_id >= dev->data->nb_tx_queues)
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return -EINVAL;
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txq = dev->data->tx_queues[tx_queue_id];
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/* Init the RX tail register. */
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txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(tx_queue_id);
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IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
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IAVF_WRITE_FLUSH(hw);
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/* Ready to switch the queue on */
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err = ice_dcf_switch_queue(&ad->real_hw, tx_queue_id, false, true);
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if (err) {
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PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
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tx_queue_id);
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return err;
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}
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dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
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return 0;
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}
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static int
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ice_dcf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
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{
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struct ice_dcf_adapter *ad = dev->data->dev_private;
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struct ice_dcf_hw *hw = &ad->real_hw;
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struct ice_tx_queue *txq;
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int err;
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if (tx_queue_id >= dev->data->nb_tx_queues)
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return -EINVAL;
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err = ice_dcf_switch_queue(hw, tx_queue_id, false, false);
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if (err) {
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PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
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tx_queue_id);
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return err;
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}
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txq = dev->data->tx_queues[tx_queue_id];
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txq->tx_rel_mbufs(txq);
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reset_tx_queue(txq);
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dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
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return 0;
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}
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static int
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ice_dcf_start_queues(struct rte_eth_dev *dev)
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{
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struct ice_rx_queue *rxq;
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struct ice_tx_queue *txq;
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int nb_rxq = 0;
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int nb_txq, i;
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for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
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txq = dev->data->tx_queues[nb_txq];
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if (txq->tx_deferred_start)
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continue;
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if (ice_dcf_tx_queue_start(dev, nb_txq) != 0) {
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PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_txq);
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goto tx_err;
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}
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}
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for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
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rxq = dev->data->rx_queues[nb_rxq];
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if (rxq->rx_deferred_start)
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continue;
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if (ice_dcf_rx_queue_start(dev, nb_rxq) != 0) {
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PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_rxq);
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goto rx_err;
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}
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}
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return 0;
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/* stop the started queues if failed to start all queues */
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rx_err:
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for (i = 0; i < nb_rxq; i++)
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ice_dcf_rx_queue_stop(dev, i);
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tx_err:
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for (i = 0; i < nb_txq; i++)
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ice_dcf_tx_queue_stop(dev, i);
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return -1;
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}
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static int
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ice_dcf_dev_start(struct rte_eth_dev *dev)
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{
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@ -267,15 +533,59 @@ ice_dcf_dev_start(struct rte_eth_dev *dev)
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return ret;
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}
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if (dev->data->dev_conf.intr_conf.rxq != 0) {
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rte_intr_disable(intr_handle);
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rte_intr_enable(intr_handle);
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}
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ret = ice_dcf_start_queues(dev);
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if (ret) {
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PMD_DRV_LOG(ERR, "Failed to enable queues");
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return ret;
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}
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dev->data->dev_link.link_status = ETH_LINK_UP;
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return 0;
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}
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static void
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ice_dcf_stop_queues(struct rte_eth_dev *dev)
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{
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struct ice_dcf_adapter *ad = dev->data->dev_private;
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struct ice_dcf_hw *hw = &ad->real_hw;
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struct ice_rx_queue *rxq;
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struct ice_tx_queue *txq;
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int ret, i;
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/* Stop All queues */
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ret = ice_dcf_disable_queues(hw);
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if (ret)
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PMD_DRV_LOG(WARNING, "Fail to stop queues");
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for (i = 0; i < dev->data->nb_tx_queues; i++) {
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txq = dev->data->tx_queues[i];
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if (!txq)
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continue;
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txq->tx_rel_mbufs(txq);
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reset_tx_queue(txq);
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dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
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}
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for (i = 0; i < dev->data->nb_rx_queues; i++) {
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rxq = dev->data->rx_queues[i];
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if (!rxq)
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continue;
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rxq->rx_rel_mbufs(rxq);
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reset_rx_queue(rxq);
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dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
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}
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}
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static void
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ice_dcf_dev_stop(struct rte_eth_dev *dev)
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{
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struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
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struct rte_intr_handle *intr_handle = dev->intr_handle;
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struct ice_adapter *ad = &dcf_ad->parent;
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if (ad->pf.adapter_stopped == 1) {
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@ -283,6 +593,14 @@ ice_dcf_dev_stop(struct rte_eth_dev *dev)
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return;
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}
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ice_dcf_stop_queues(dev);
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rte_intr_efd_disable(intr_handle);
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if (intr_handle->intr_vec) {
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rte_free(intr_handle->intr_vec);
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intr_handle->intr_vec = NULL;
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}
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dev->data->dev_link.link_status = ETH_LINK_DOWN;
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ad->pf.adapter_stopped = 1;
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}
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@ -477,6 +795,10 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = {
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.tx_queue_setup = ice_tx_queue_setup,
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.rx_queue_release = ice_rx_queue_release,
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.tx_queue_release = ice_tx_queue_release,
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.rx_queue_start = ice_dcf_rx_queue_start,
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.tx_queue_start = ice_dcf_tx_queue_start,
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.rx_queue_stop = ice_dcf_rx_queue_stop,
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.tx_queue_stop = ice_dcf_tx_queue_stop,
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.link_update = ice_dcf_link_update,
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.stats_get = ice_dcf_stats_get,
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.stats_reset = ice_dcf_stats_reset,
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