regex/mlx5: add send queue
This commit introduce the SQ creation. The SQ is used for enqueuing a job. In order to support out of order matches, we create number os SQ per one application QP. Signed-off-by: Ori Kam <orika@mellanox.com>
This commit is contained in:
Ori Kam
Thomas Monjalon
parent
fbc8c7003b
commit
92f2c6a30f
@ -21,6 +21,7 @@ struct mlx5_regex_sq {
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uint32_t dbr_umem; /* Door bell record umem id. */
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uint8_t *wqe; /* The SQ ring buffer. */
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struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */
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uint32_t *dbr;
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};
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struct mlx5_regex_cq {
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@ -30,6 +31,7 @@ struct mlx5_regex_cq {
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uint32_t dbr_umem; /* Door bell record umem id. */
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volatile struct mlx5_cqe *cqe; /* The CQ ring buffer. */
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struct mlx5dv_devx_umem *cqe_umem; /* CQ buffer umem. */
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uint32_t *dbr;
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};
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struct mlx5_regex_qp {
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@ -105,6 +105,9 @@ regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)
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goto error;
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}
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cq->dbr_umem = mlx5_os_get_umem_id(dbr_page->umem);
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cq->dbr = (uint32_t *)((uintptr_t)dbr_page->dbrs +
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(uintptr_t)cq->dbr_offset);
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buf = rte_calloc(NULL, 1, sizeof(struct mlx5_cqe) * cq_size, 4096);
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if (!buf) {
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DRV_LOG(ERR, "Can't allocate cqe buffer.");
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@ -145,6 +148,170 @@ error:
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return -rte_errno;
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}
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#ifdef HAVE_IBV_FLOW_DV_SUPPORT
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static int
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regex_get_pdn(void *pd, uint32_t *pdn)
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{
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struct mlx5dv_obj obj;
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struct mlx5dv_pd pd_info;
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int ret = 0;
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obj.pd.in = pd;
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obj.pd.out = &pd_info;
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ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
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if (ret) {
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DRV_LOG(DEBUG, "Fail to get PD object info");
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return ret;
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}
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*pdn = pd_info.pdn;
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return 0;
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}
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#endif
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/**
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* create the SQ object.
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*
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* @param priv
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* Pointer to the priv object.
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* @param qp
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* Pointer to the QP element
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* @param q_ind
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* The index of the queue.
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* @param log_nb_desc
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* Log 2 of the number of descriptors to be used.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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static int
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regex_ctrl_create_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
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uint16_t q_ind, uint16_t log_nb_desc)
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{
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#ifdef HAVE_IBV_FLOW_DV_SUPPORT
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struct mlx5_devx_create_sq_attr attr = { 0 };
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struct mlx5_devx_modify_sq_attr modify_attr = { 0 };
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struct mlx5_devx_wq_attr *wq_attr = &attr.wq_attr;
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struct mlx5_devx_dbr_page *dbr_page = NULL;
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struct mlx5_regex_sq *sq = &qp->sqs[q_ind];
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void *buf = NULL;
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uint32_t sq_size;
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uint32_t pd_num = 0;
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int ret;
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sq->log_nb_desc = log_nb_desc;
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sq_size = 1 << sq->log_nb_desc;
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sq->dbr_offset = mlx5_get_dbr(priv->ctx, &priv->dbrpgs, &dbr_page);
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if (sq->dbr_offset < 0) {
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DRV_LOG(ERR, "Can't allocate sq door bell record.");
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rte_errno = ENOMEM;
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goto error;
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}
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sq->dbr_umem = mlx5_os_get_umem_id(dbr_page->umem);
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sq->dbr = (uint32_t *)((uintptr_t)dbr_page->dbrs +
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(uintptr_t)sq->dbr_offset);
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buf = rte_calloc(NULL, 1, 64 * sq_size, 4096);
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if (!buf) {
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DRV_LOG(ERR, "Can't allocate wqe buffer.");
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rte_errno = ENOMEM;
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goto error;
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}
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sq->wqe = buf;
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sq->wqe_umem = mlx5_glue->devx_umem_reg(priv->ctx, buf, 64 * sq_size,
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7);
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if (!sq->wqe_umem) {
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DRV_LOG(ERR, "Can't register wqe mem.");
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rte_errno = ENOMEM;
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goto error;
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}
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attr.state = MLX5_SQC_STATE_RST;
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attr.tis_lst_sz = 0;
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attr.tis_num = 0;
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attr.user_index = q_ind;
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attr.cqn = qp->cq.obj->id;
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wq_attr->uar_page = priv->uar->page_id;
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regex_get_pdn(priv->pd, &pd_num);
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wq_attr->pd = pd_num;
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wq_attr->wq_type = MLX5_WQ_TYPE_CYCLIC;
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wq_attr->dbr_umem_id = sq->dbr_umem;
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wq_attr->dbr_addr = sq->dbr_offset;
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wq_attr->dbr_umem_valid = 1;
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wq_attr->wq_umem_id = mlx5_os_get_umem_id(sq->wqe_umem);
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wq_attr->wq_umem_offset = 0;
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wq_attr->wq_umem_valid = 1;
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wq_attr->log_wq_stride = 6;
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wq_attr->log_wq_sz = sq->log_nb_desc;
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sq->obj = mlx5_devx_cmd_create_sq(priv->ctx, &attr);
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if (!sq->obj) {
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DRV_LOG(ERR, "Can't create sq object.");
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rte_errno = ENOMEM;
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goto error;
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}
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modify_attr.state = MLX5_SQC_STATE_RDY;
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ret = mlx5_devx_cmd_modify_sq(sq->obj, &modify_attr);
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if (ret) {
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DRV_LOG(ERR, "Can't change sq state to ready.");
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rte_errno = ENOMEM;
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goto error;
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}
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return 0;
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error:
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if (sq->wqe_umem)
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mlx5_glue->devx_umem_dereg(sq->wqe_umem);
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if (buf)
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rte_free(buf);
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if (sq->dbr_offset)
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mlx5_release_dbr(&priv->dbrpgs, sq->dbr_umem, sq->dbr_offset);
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return -rte_errno;
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#else
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(void)priv;
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(void)qp;
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(void)q_ind;
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(void)log_nb_desc;
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DRV_LOG(ERR, "Cannot get pdn - no DV support.");
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return -ENOTSUP;
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#endif
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}
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/**
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* Destroy the SQ object.
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*
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* @param priv
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* Pointer to the priv object.
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* @param qp
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* Pointer to the QP element
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* @param q_ind
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* The index of the queue.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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static int
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regex_ctrl_destroy_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
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uint16_t q_ind)
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{
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struct mlx5_regex_sq *sq = &qp->sqs[q_ind];
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if (sq->wqe_umem) {
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mlx5_glue->devx_umem_dereg(sq->wqe_umem);
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sq->wqe_umem = NULL;
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}
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if (sq->wqe) {
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rte_free((void *)(uintptr_t)sq->wqe);
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sq->wqe = NULL;
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}
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if (sq->dbr_offset) {
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mlx5_release_dbr(&priv->dbrpgs, sq->dbr_umem, sq->dbr_offset);
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sq->dbr_offset = -1;
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}
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if (sq->obj) {
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mlx5_devx_cmd_destroy(sq->obj);
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sq->obj = NULL;
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}
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return 0;
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}
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/**
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* Setup the qp.
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*
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@ -164,7 +331,9 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
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{
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struct mlx5_regex_priv *priv = dev->data->dev_private;
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struct mlx5_regex_qp *qp;
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int i;
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int ret;
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uint16_t log_desc;
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qp = &priv->qps[qp_ind];
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qp->flags = cfg->qp_conf_flags;
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@ -181,15 +350,25 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
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rte_errno = ENOMEM;
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return -rte_errno;
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}
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log_desc = rte_log2_u32(qp->nb_desc / qp->nb_obj);
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ret = regex_ctrl_create_cq(priv, &qp->cq);
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if (ret) {
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DRV_LOG(ERR, "Can't create cq.");
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goto error;
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}
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for (i = 0; i < qp->nb_obj; i++) {
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ret = regex_ctrl_create_sq(priv, qp, i, log_desc);
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if (ret) {
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DRV_LOG(ERR, "Can't create sq.");
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goto error;
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}
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}
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return 0;
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error:
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regex_ctrl_destroy_cq(priv, &qp->cq);
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for (i = 0; i < qp->nb_obj; i++)
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ret = regex_ctrl_destroy_sq(priv, qp, i);
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return -rte_errno;
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}
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