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net/octeontx2: support CN98xx

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New cn98xx SOC comes up with two NIX blocks wrt
cn96xx, cn93xx, to achieve higher performance.
Also the no of cores increased to 36 from 24.

Adding support for cn98xx where need a logic to
detect if the LF is attached to NIX0 or NIX1 and
then accordingly use the respective NIX block.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Harman Kalra 2020-06-24 18:16:48 +05:30 committed by Ferruh Yigit
parent 420bbdae89
commit 9311beeea4
6 changed files with 25 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
config/arm/meson.build
View File

@ -82,7 +82,7 @@ flags_thunderx2_extra = [
flags_octeontx2_extra = [
['RTE_MACHINE', '"octeontx2"'],
['RTE_MAX_NUMA_NODES', 1],
['RTE_MAX_LCORE', 24],
['RTE_MAX_LCORE', 36],
['RTE_ARM_FEATURE_ATOMICS', true],
['RTE_EAL_IGB_UIO', false],
['RTE_USE_C11_MEM_MODEL', true]]

2
config/defconfig_arm64-octeontx2-linuxapp-gcc
View File

@ -7,7 +7,7 @@
CONFIG_RTE_MACHINE="octeontx2"
CONFIG_RTE_MAX_NUMA_NODES=1
CONFIG_RTE_MAX_LCORE=24
CONFIG_RTE_MAX_LCORE=36
CONFIG_RTE_ARM_FEATURE_ATOMICS=y
# Doesn't support NUMA

1
doc/guides/platform/octeontx2.rst
View File

@ -13,6 +13,7 @@ More information about OCTEON TX2 SoC can be found at `Marvell Official Website
Supported OCTEON TX2 SoCs
-------------------------
- CN98xx
- CN96xx
- CN93xx

4
doc/guides/rel_notes/release_20_08.rst
View File

@ -80,6 +80,10 @@ New Features
* Added support for virtio queue statistics.
* Added support for MTU update.
* **Updated Marvell octeontx2 ethdev PMD.**
Updated Marvell octeontx2 driver with cn98xx support.
* **Added support for BPF_ABS/BPF_IND load instructions.**
Added support for two BPF non-generic instructions:

3
drivers/common/octeontx2/hw/otx2_rvu.h
View File

@ -134,11 +134,12 @@
#define RVU_BLOCK_ADDR_RVUM (0x0ull)
#define RVU_BLOCK_ADDR_LMT (0x1ull)
#define RVU_BLOCK_ADDR_NPA (0x3ull)
#define RVU_BLOCK_ADDR_NIX0 (0x4ull)
#define RVU_BLOCK_ADDR_NIX1 (0x5ull)
#define RVU_BLOCK_ADDR_NPC (0x6ull)
#define RVU_BLOCK_ADDR_SSO (0x7ull)
#define RVU_BLOCK_ADDR_SSOW (0x8ull)
#define RVU_BLOCK_ADDR_TIM (0x9ull)
#define RVU_BLOCK_ADDR_NIX0 (0x4ull)
#define RVU_BLOCK_ADDR_CPT0 (0xaull)
#define RVU_BLOCK_ADDR_NDC0 (0xcull)
#define RVU_BLOCK_ADDR_NDC1 (0xdull)

17
drivers/net/octeontx2/otx2_ethdev.c
View File

@ -2177,6 +2177,20 @@ otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
return false;
}
static inline uint64_t
nix_get_blkaddr(struct otx2_eth_dev *dev)
{
uint64_t reg;
/* Reading the discovery register to know which NIX is the LF
* attached to.
*/
reg = otx2_read64(dev->bar2 +
RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));
return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;
}
static int
otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
{
@ -2236,7 +2250,6 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
dev->configured = 0;
dev->drv_inited = true;
dev->ptype_disable = 0;
dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
/* Attach NIX LF */
@ -2244,6 +2257,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
if (rc)
goto otx2_npa_uninit;
dev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20);
/* Get NIX MSIX offset */
rc = nix_lf_get_msix_offset(dev);
if (rc)