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eal/ppc: adapt CPU flags check to the arch

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The structure feature_entry does not need leaf/subleaf
which were copied from x86 CPUID implementation.

On x86, a valid flag is detected with the non-zero leaf value.
This check is replaced by a check with a dummy "none" register.

Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
This commit is contained in:
Thomas Monjalon 2016-02-03 00:10:25 +01:00
parent 5851aa9171
commit 9369dcb7a6
1 changed files with 47 additions and 57 deletions
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104
lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c
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@ -43,70 +43,66 @@
/* software based registers */
enum cpu_register_t {
REG_HWCAP = 0,
REG_NONE = 0,
REG_HWCAP,
REG_HWCAP2,
REG_MAX
};
typedef uint32_t cpuid_registers_t[4];
typedef uint32_t hwcap_registers_t[REG_MAX];
/**
* Struct to hold a processor feature entry
*/
struct feature_entry {
uint32_t leaf; /**< cpuid leaf */
uint32_t subleaf; /**< cpuid subleaf */
uint32_t reg; /**< cpuid register */
uint32_t bit; /**< cpuid register bit */
uint32_t reg;
uint32_t bit;
#define CPU_FLAG_NAME_MAX_LEN 64
char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */
char name[CPU_FLAG_NAME_MAX_LEN];
};
#define FEAT_DEF(name, leaf, subleaf, reg, bit) \
[RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },
#define FEAT_DEF(name, reg, bit) \
[RTE_CPUFLAG_##name] = {reg, bit, #name},
const struct feature_entry rte_cpu_feature_table[] = {
FEAT_DEF(PPC_LE, 0x00000001, 0, REG_HWCAP, 0)
FEAT_DEF(TRUE_LE, 0x00000001, 0, REG_HWCAP, 1)
FEAT_DEF(PSERIES_PERFMON_COMPAT, 0x00000001, 0, REG_HWCAP, 6)
FEAT_DEF(VSX, 0x00000001, 0, REG_HWCAP, 7)
FEAT_DEF(ARCH_2_06, 0x00000001, 0, REG_HWCAP, 8)
FEAT_DEF(POWER6_EXT, 0x00000001, 0, REG_HWCAP, 9)
FEAT_DEF(DFP, 0x00000001, 0, REG_HWCAP, 10)
FEAT_DEF(PA6T, 0x00000001, 0, REG_HWCAP, 11)
FEAT_DEF(ARCH_2_05, 0x00000001, 0, REG_HWCAP, 12)
FEAT_DEF(ICACHE_SNOOP, 0x00000001, 0, REG_HWCAP, 13)
FEAT_DEF(SMT, 0x00000001, 0, REG_HWCAP, 14)
FEAT_DEF(BOOKE, 0x00000001, 0, REG_HWCAP, 15)
FEAT_DEF(CELLBE, 0x00000001, 0, REG_HWCAP, 16)
FEAT_DEF(POWER5_PLUS, 0x00000001, 0, REG_HWCAP, 17)
FEAT_DEF(POWER5, 0x00000001, 0, REG_HWCAP, 18)
FEAT_DEF(POWER4, 0x00000001, 0, REG_HWCAP, 19)
FEAT_DEF(NOTB, 0x00000001, 0, REG_HWCAP, 20)
FEAT_DEF(EFP_DOUBLE, 0x00000001, 0, REG_HWCAP, 21)
FEAT_DEF(EFP_SINGLE, 0x00000001, 0, REG_HWCAP, 22)
FEAT_DEF(SPE, 0x00000001, 0, REG_HWCAP, 23)
FEAT_DEF(UNIFIED_CACHE, 0x00000001, 0, REG_HWCAP, 24)
FEAT_DEF(4xxMAC, 0x00000001, 0, REG_HWCAP, 25)
FEAT_DEF(MMU, 0x00000001, 0, REG_HWCAP, 26)
FEAT_DEF(FPU, 0x00000001, 0, REG_HWCAP, 27)
FEAT_DEF(ALTIVEC, 0x00000001, 0, REG_HWCAP, 28)
FEAT_DEF(PPC601, 0x00000001, 0, REG_HWCAP, 29)
FEAT_DEF(PPC64, 0x00000001, 0, REG_HWCAP, 30)
FEAT_DEF(PPC32, 0x00000001, 0, REG_HWCAP, 31)
FEAT_DEF(TAR, 0x00000001, 0, REG_HWCAP2, 26)
FEAT_DEF(LSEL, 0x00000001, 0, REG_HWCAP2, 27)
FEAT_DEF(EBB, 0x00000001, 0, REG_HWCAP2, 28)
FEAT_DEF(DSCR, 0x00000001, 0, REG_HWCAP2, 29)
FEAT_DEF(HTM, 0x00000001, 0, REG_HWCAP2, 30)
FEAT_DEF(ARCH_2_07, 0x00000001, 0, REG_HWCAP2, 31)
FEAT_DEF(PPC_LE, REG_HWCAP, 0)
FEAT_DEF(TRUE_LE, REG_HWCAP, 1)
FEAT_DEF(PSERIES_PERFMON_COMPAT, REG_HWCAP, 6)
FEAT_DEF(VSX, REG_HWCAP, 7)
FEAT_DEF(ARCH_2_06, REG_HWCAP, 8)
FEAT_DEF(POWER6_EXT, REG_HWCAP, 9)
FEAT_DEF(DFP, REG_HWCAP, 10)
FEAT_DEF(PA6T, REG_HWCAP, 11)
FEAT_DEF(ARCH_2_05, REG_HWCAP, 12)
FEAT_DEF(ICACHE_SNOOP, REG_HWCAP, 13)
FEAT_DEF(SMT, REG_HWCAP, 14)
FEAT_DEF(BOOKE, REG_HWCAP, 15)
FEAT_DEF(CELLBE, REG_HWCAP, 16)
FEAT_DEF(POWER5_PLUS, REG_HWCAP, 17)
FEAT_DEF(POWER5, REG_HWCAP, 18)
FEAT_DEF(POWER4, REG_HWCAP, 19)
FEAT_DEF(NOTB, REG_HWCAP, 20)
FEAT_DEF(EFP_DOUBLE, REG_HWCAP, 21)
FEAT_DEF(EFP_SINGLE, REG_HWCAP, 22)
FEAT_DEF(SPE, REG_HWCAP, 23)
FEAT_DEF(UNIFIED_CACHE, REG_HWCAP, 24)
FEAT_DEF(4xxMAC, REG_HWCAP, 25)
FEAT_DEF(MMU, REG_HWCAP, 26)
FEAT_DEF(FPU, REG_HWCAP, 27)
FEAT_DEF(ALTIVEC, REG_HWCAP, 28)
FEAT_DEF(PPC601, REG_HWCAP, 29)
FEAT_DEF(PPC64, REG_HWCAP, 30)
FEAT_DEF(PPC32, REG_HWCAP, 31)
FEAT_DEF(TAR, REG_HWCAP2, 26)
FEAT_DEF(LSEL, REG_HWCAP2, 27)
FEAT_DEF(EBB, REG_HWCAP2, 28)
FEAT_DEF(DSCR, REG_HWCAP2, 29)
FEAT_DEF(HTM, REG_HWCAP2, 30)
FEAT_DEF(ARCH_2_07, REG_HWCAP2, 31)
};
/*
* Read AUXV software register and get cpu features for Power
*/
static void
rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
__attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)
rte_cpu_get_features(hwcap_registers_t out)
{
int auxv_fd;
Elf64_auxv_t auxv;
@ -129,22 +125,16 @@ int
rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
{
const struct feature_entry *feat;
cpuid_registers_t regs = {0};
hwcap_registers_t regs = {0};
if (feature >= RTE_CPUFLAG_NUMFLAGS)
/* Flag does not match anything in the feature tables */
return -ENOENT;
feat = &rte_cpu_feature_table[feature];
if (!feat->leaf)
/* This entry in the table wasn't filled out! */
if (feat->reg == REG_NONE)
return -EFAULT;
/* get the cpuid leaf containing the desired feature */
rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
/* check if the feature is enabled */
rte_cpu_get_features(regs);
return (regs[feat->reg] >> feat->bit) & 1;
}