net/enic: enable overlay offload for VXLAN and GENEVE
Recent NIC models support overlay offload. The overlay offload feature enables the following on the NIC. - Rx/Tx checksum offloads for both inner and outer packets. - Rx inner packet type classification. - TSO. - Inner RSS. TX descriptors do not require any changes, except the header length for TSO. The NIC parses outer/inner packets and performs offloads on them as necessary. The header length for tunneled TSO includes both inner and outer headers. The NIC actually parses and performs the above for NVGRE as well. DPDK currently has no offload flags for NVGRE, and the hardware has no controls to individually enable tunnel types either. So do nothing for now. The driver enables overlay offload by default. Add a devargs 'disable-overlay=<0|1>' to allow the app to disable it. Also update the enic guide doc. Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com> Reviewed-by: John Daley <johndale@cisco.com>
This commit is contained in:
Hyong Youb Kim
Ferruh Yigit
parent
8055b534d6
commit
93fb21fdbe
@ -254,6 +254,54 @@ Generic Flow API is supported. The baseline support is:
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More features may be added in future firmware and new versions of the VIC.
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Please refer to the release notes.
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.. _overlay_offload:
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Overlay Offload
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---------------
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Recent hardware models support overlay offload. When enabled, the NIC performs
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the following operations for VXLAN, NVGRE, and GENEVE packets. In all cases,
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inner and outer packets can be IPv4 or IPv6.
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- TSO for VXLAN and GENEVE packets.
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Hardware supports NVGRE TSO, but DPDK currently has no NVGRE offload flags.
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- Tx checksum offloads.
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The NIC fills in IPv4/UDP/TCP checksums for both inner and outer packets.
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- Rx checksum offloads.
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The NIC validates IPv4/UDP/TCP checksums of both inner and outer packets.
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Good checksum flags (e.g. ``PKT_RX_L4_CKSUM_GOOD``) indicate that the inner
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packet has the correct checksum, and if applicable, the outer packet also
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has the correct checksum. Bad checksum flags (e.g. ``PKT_RX_L4_CKSUM_BAD``)
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indicate that the inner and/or outer packets have invalid checksum values.
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- Inner Rx packet type classification
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PMD sets inner L3/L4 packet types (e.g. ``RTE_PTYPE_INNER_L4_TCP``), and
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``RTE_PTYPE_TUNNEL_GRENAT`` to indicate that the packet is tunneled.
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PMD does not set L3/L4 packet types for outer packets.
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- Inner RSS
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RSS hash calculation, therefore queue selection, is done on inner packets.
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In order to enable overlay offload, the 'Enable VXLAN' box should be checked
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via CIMC or UCSM followed by a reboot of the server. When PMD successfully
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enables overlay offload, it prints the following message on the console.
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.. code-block:: console
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Overlay offload is enabled
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By default, PMD enables overlay offload if hardware supports it. To disable
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it, set ``devargs`` parameter ``disable-overlay=1``. For example::
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-w 12:00.0,disable-overlay=1
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.. _enic_limitations:
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Limitations
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@ -376,6 +424,11 @@ Supported features
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- MTU update
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- SR-IOV on UCS managed servers connected to Fabric Interconnects
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- Flow API
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- Overlay offload
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- Rx/Tx checksum offloads for VXLAN, NVGRE, GENEVE
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- TSO for VXLAN and GENEVE packets
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- Inner RSS
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Known bugs and unsupported features in this release
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---------------------------------------------------
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@ -1062,3 +1062,36 @@ int vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,
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return ret;
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}
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int vnic_dev_overlay_offload_ctrl(struct vnic_dev *vdev, u8 overlay, u8 config)
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{
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u64 a0 = overlay;
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u64 a1 = config;
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int wait = 1000;
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return vnic_dev_cmd(vdev, CMD_OVERLAY_OFFLOAD_CTRL, &a0, &a1, wait);
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}
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int vnic_dev_overlay_offload_cfg(struct vnic_dev *vdev, u8 overlay,
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u16 vxlan_udp_port_number)
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{
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u64 a1 = vxlan_udp_port_number;
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u64 a0 = overlay;
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int wait = 1000;
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return vnic_dev_cmd(vdev, CMD_OVERLAY_OFFLOAD_CFG, &a0, &a1, wait);
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}
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int vnic_dev_capable_vxlan(struct vnic_dev *vdev)
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{
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u64 a0 = VIC_FEATURE_VXLAN;
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u64 a1 = 0;
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int wait = 1000;
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int ret;
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ret = vnic_dev_cmd(vdev, CMD_GET_SUPP_FEATURE_VER, &a0, &a1, wait);
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/* 1 if the NIC can do VXLAN for both IPv4 and IPv6 with multiple WQs */
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return ret == 0 &&
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(a1 & (FEATURE_VXLAN_IPV6 | FEATURE_VXLAN_MULTI_WQ)) ==
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(FEATURE_VXLAN_IPV6 | FEATURE_VXLAN_MULTI_WQ);
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}
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@ -179,10 +179,9 @@ int vnic_dev_deinit_done(struct vnic_dev *vdev, int *status);
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int vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr);
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int vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,
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struct filter_v2 *data, struct filter_action_v2 *action_v2);
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#ifdef ENIC_VXLAN
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int vnic_dev_overlay_offload_enable_disable(struct vnic_dev *vdev,
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int vnic_dev_overlay_offload_ctrl(struct vnic_dev *vdev,
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u8 overlay, u8 config);
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int vnic_dev_overlay_offload_cfg(struct vnic_dev *vdev, u8 overlay,
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u16 vxlan_udp_port_number);
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#endif
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int vnic_dev_capable_vxlan(struct vnic_dev *vdev);
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#endif /* _VNIC_DEV_H_ */
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@ -1080,6 +1080,18 @@ typedef enum {
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VIC_FEATURE_MAX,
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} vic_feature_t;
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/*
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* These flags are used in args[1] of devcmd CMD_GET_SUPP_FEATURE_VER
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* to indicate the host driver about the VxLAN and Multi WQ features
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* supported
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*/
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#define FEATURE_VXLAN_IPV6_INNER (1 << 0)
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#define FEATURE_VXLAN_IPV6_OUTER (1 << 1)
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#define FEATURE_VXLAN_MULTI_WQ (1 << 2)
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#define FEATURE_VXLAN_IPV6 (FEATURE_VXLAN_IPV6_INNER | \
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FEATURE_VXLAN_IPV6_OUTER)
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/*
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* CMD_CONFIG_GRPINTR subcommands
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*/
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@ -44,6 +44,7 @@ struct vnic_wq_buf {
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struct vnic_wq {
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unsigned int index;
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uint64_t tx_offload_notsup_mask;
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struct vnic_dev *vdev;
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struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
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struct vnic_dev_ring ring;
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@ -17,6 +17,7 @@
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#include "vnic_rss.h"
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#include "enic_res.h"
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#include "cq_enet_desc.h"
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#include <stdbool.h>
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#include <sys/queue.h>
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#include <rte_spinlock.h>
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@ -101,6 +102,7 @@ struct enic {
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struct vnic_dev *vdev;
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unsigned int port_id;
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bool overlay_offload;
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struct rte_eth_dev *rte_dev;
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struct enic_fdir fdir;
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char bdf_name[ENICPMD_BDF_LENGTH];
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@ -119,6 +121,8 @@ struct enic {
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u8 adv_filters;
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u32 flow_filter_mode;
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u8 filter_actions; /* HW supported actions */
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bool vxlan;
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bool disable_overlay; /* devargs disable_overlay=1 */
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unsigned int flags;
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unsigned int priv_flags;
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@ -169,6 +173,10 @@ struct enic {
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uint64_t rss_hf; /* ETH_RSS flags */
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union vnic_rss_key rss_key;
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union vnic_rss_cpu rss_cpu;
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uint64_t rx_offload_capa; /* DEV_RX_OFFLOAD flags */
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uint64_t tx_offload_capa; /* DEV_TX_OFFLOAD flags */
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uint64_t tx_offload_mask; /* PKT_TX flags accepted */
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};
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/* Compute ethdev's max packet size from MTU */
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@ -11,6 +11,7 @@
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#include <rte_bus_pci.h>
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#include <rte_ethdev_driver.h>
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#include <rte_ethdev_pci.h>
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#include <rte_kvargs.h>
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#include <rte_string_fns.h>
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#include "vnic_intr.h"
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@ -39,18 +40,7 @@ static const struct rte_pci_id pci_id_enic_map[] = {
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{.vendor_id = 0, /* sentinel */},
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};
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#define ENIC_TX_OFFLOAD_CAPA ( \
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DEV_TX_OFFLOAD_VLAN_INSERT | \
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DEV_TX_OFFLOAD_IPV4_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_TSO)
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#define ENIC_RX_OFFLOAD_CAPA ( \
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DEV_RX_OFFLOAD_VLAN_STRIP | \
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DEV_RX_OFFLOAD_IPV4_CKSUM | \
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DEV_RX_OFFLOAD_UDP_CKSUM | \
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DEV_RX_OFFLOAD_TCP_CKSUM)
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#define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay"
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RTE_INIT(enicpmd_init_log);
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static void
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@ -484,8 +474,8 @@ static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
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*/
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device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu);
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device_info->max_mac_addrs = ENIC_MAX_MAC_ADDR;
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device_info->rx_offload_capa = ENIC_RX_OFFLOAD_CAPA;
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device_info->tx_offload_capa = ENIC_TX_OFFLOAD_CAPA;
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device_info->rx_offload_capa = enic->rx_offload_capa;
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device_info->tx_offload_capa = enic->tx_offload_capa;
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device_info->default_rxconf = (struct rte_eth_rxconf) {
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.rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH
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};
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@ -734,7 +724,7 @@ static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev,
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* Except VLAN stripping (port setting), all the checksum offloads
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* are always enabled.
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*/
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conf->offloads = ENIC_RX_OFFLOAD_CAPA;
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conf->offloads = enic->rx_offload_capa;
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if (!enic->ig_vlan_strip_en)
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conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
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/* rx_thresh and other fields are not applicable for enic */
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@ -749,7 +739,7 @@ static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev,
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ENICPMD_FUNC_TRACE();
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qinfo->nb_desc = enic->config.wq_desc_count;
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memset(&qinfo->conf, 0, sizeof(qinfo->conf));
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qinfo->conf.offloads = ENIC_TX_OFFLOAD_CAPA; /* not configurable */
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qinfo->conf.offloads = enic->tx_offload_capa;
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/* tx_thresh, and all the other fields are not applicable for enic */
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}
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@ -824,6 +814,49 @@ static const struct eth_dev_ops enicpmd_eth_dev_ops = {
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.rss_hash_update = enicpmd_dev_rss_hash_update,
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};
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static int enic_parse_disable_overlay(__rte_unused const char *key,
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const char *value,
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void *opaque)
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{
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struct enic *enic;
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enic = (struct enic *)opaque;
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if (strcmp(value, "0") == 0) {
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enic->disable_overlay = false;
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} else if (strcmp(value, "1") == 0) {
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enic->disable_overlay = true;
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} else {
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dev_err(enic, "Invalid value for " ENIC_DEVARG_DISABLE_OVERLAY
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": expected=0|1 given=%s\n", value);
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return -EINVAL;
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}
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return 0;
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}
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static int enic_check_devargs(struct rte_eth_dev *dev)
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{
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static const char *const valid_keys[] = {
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ENIC_DEVARG_DISABLE_OVERLAY, NULL};
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struct enic *enic = pmd_priv(dev);
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struct rte_kvargs *kvlist;
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ENICPMD_FUNC_TRACE();
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enic->disable_overlay = false;
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if (!dev->device->devargs)
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return 0;
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kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
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if (!kvlist)
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return -EINVAL;
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if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY,
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enic_parse_disable_overlay, enic) < 0) {
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rte_kvargs_free(kvlist);
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return -EINVAL;
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}
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rte_kvargs_free(kvlist);
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return 0;
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}
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struct enic *enicpmd_list_head = NULL;
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/* Initialize the driver
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* It returns 0 on success.
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@ -833,6 +866,7 @@ static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev)
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struct rte_pci_device *pdev;
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struct rte_pci_addr *addr;
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struct enic *enic = pmd_priv(eth_dev);
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int err;
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ENICPMD_FUNC_TRACE();
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@ -851,6 +885,9 @@ static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev)
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snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x",
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addr->domain, addr->bus, addr->devid, addr->function);
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err = enic_check_devargs(eth_dev);
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if (err)
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return err;
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return enic_probe(enic);
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}
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@ -876,3 +913,5 @@ static struct rte_pci_driver rte_enic_pmd = {
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RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd);
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RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map);
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RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci");
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RTE_PMD_REGISTER_PARAM_STRING(net_enic,
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ENIC_DEVARG_DISABLE_OVERLAY "=<0|1> ");
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@ -244,6 +244,9 @@ void enic_init_vnic_resources(struct enic *enic)
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enic_cq_wq(enic, index),
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error_interrupt_enable,
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error_interrupt_offset);
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/* Compute unsupported ol flags for enic_prep_pkts() */
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enic->wq[index].tx_offload_notsup_mask =
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PKT_TX_OFFLOAD_MASK ^ enic->tx_offload_mask;
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cq_idx = enic_cq_wq(enic, index);
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vnic_cq_init(&enic->cq[cq_idx],
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@ -1546,6 +1549,27 @@ static int enic_dev_init(struct enic *enic)
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/* set up link status checking */
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vnic_dev_notify_set(enic->vdev, -1); /* No Intr for notify */
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enic->overlay_offload = false;
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if (!enic->disable_overlay && enic->vxlan &&
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/* 'VXLAN feature' enables VXLAN, NVGRE, and GENEVE. */
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vnic_dev_overlay_offload_ctrl(enic->vdev,
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OVERLAY_FEATURE_VXLAN,
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OVERLAY_OFFLOAD_ENABLE) == 0) {
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enic->tx_offload_capa |=
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
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DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
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DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
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/*
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* Do not add PKT_TX_OUTER_{IPV4,IPV6} as they are not
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* 'offload' flags (i.e. not part of PKT_TX_OFFLOAD_MASK).
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*/
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enic->tx_offload_mask |=
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PKT_TX_OUTER_IP_CKSUM |
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PKT_TX_TUNNEL_MASK;
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enic->overlay_offload = true;
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dev_info(enic, "Overlay offload is enabled\n");
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}
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return 0;
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}
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@ -158,6 +158,29 @@ int enic_get_vnic_config(struct enic *enic)
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if (!ENIC_SETTING(enic, RSS))
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enic->flow_type_rss_offloads = 0;
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enic->vxlan = ENIC_SETTING(enic, VXLAN) &&
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vnic_dev_capable_vxlan(enic->vdev);
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/*
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* Default hardware capabilities. enic_dev_init() may add additional
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* flags if it enables overlay offloads.
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*/
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enic->tx_offload_capa =
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DEV_TX_OFFLOAD_VLAN_INSERT |
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DEV_TX_OFFLOAD_IPV4_CKSUM |
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DEV_TX_OFFLOAD_UDP_CKSUM |
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DEV_TX_OFFLOAD_TCP_CKSUM |
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DEV_TX_OFFLOAD_TCP_TSO;
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enic->rx_offload_capa =
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DEV_RX_OFFLOAD_VLAN_STRIP |
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DEV_RX_OFFLOAD_IPV4_CKSUM |
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DEV_RX_OFFLOAD_UDP_CKSUM |
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DEV_RX_OFFLOAD_TCP_CKSUM;
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enic->tx_offload_mask =
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PKT_TX_VLAN_PKT |
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PKT_TX_IP_CKSUM |
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PKT_TX_L4_MASK |
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PKT_TX_TCP_SEG;
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return 0;
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}
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@ -15,15 +15,6 @@
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#include <rte_ip.h>
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#include <rte_tcp.h>
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#define ENIC_TX_OFFLOAD_MASK ( \
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PKT_TX_VLAN_PKT | \
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PKT_TX_IP_CKSUM | \
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PKT_TX_L4_MASK | \
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PKT_TX_TCP_SEG)
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#define ENIC_TX_OFFLOAD_NOTSUP_MASK \
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(PKT_TX_OFFLOAD_MASK ^ ENIC_TX_OFFLOAD_MASK)
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#define RTE_PMD_USE_PREFETCH
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#ifdef RTE_PMD_USE_PREFETCH
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@ -130,30 +121,73 @@ enic_cq_rx_check_err(struct cq_desc *cqd)
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/* Lookup table to translate RX CQ flags to mbuf flags. */
|
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static inline uint32_t
|
||||
enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd)
|
||||
enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd, uint8_t tnl)
|
||||
{
|
||||
struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
|
||||
uint8_t cqrd_flags = cqrd->flags;
|
||||
/*
|
||||
* Odd-numbered entries are for tunnel packets. All packet type info
|
||||
* applies to the inner packet, and there is no info on the outer
|
||||
* packet. The outer flags in these entries exist only to avoid
|
||||
* changing enic_cq_rx_to_pkt_flags(). They are cleared from mbuf
|
||||
* afterwards.
|
||||
*
|
||||
* Also, as there is no tunnel type info (VXLAN, NVGRE, or GENEVE), set
|
||||
* RTE_PTYPE_TUNNEL_GRENAT..
|
||||
*/
|
||||
static const uint32_t cq_type_table[128] __rte_cache_aligned = {
|
||||
[0x00] = RTE_PTYPE_UNKNOWN,
|
||||
[0x20] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
|
||||
[0x21] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_NONFRAG,
|
||||
[0x22] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
|
||||
[0x23] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_UDP,
|
||||
[0x24] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
|
||||
[0x25] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_TCP,
|
||||
[0x60] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
|
||||
[0x61] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_FRAG,
|
||||
[0x62] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
|
||||
[0x63] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_UDP,
|
||||
[0x64] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
|
||||
[0x65] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_TCP,
|
||||
[0x10] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
|
||||
[0x11] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_NONFRAG,
|
||||
[0x12] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
|
||||
[0x13] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_UDP,
|
||||
[0x14] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
|
||||
[0x50] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
|
||||
[0x52] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
|
||||
[0x54] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
|
||||
[0x15] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP |
|
||||
RTE_PTYPE_TUNNEL_GRENAT |
|
||||
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
|
||||
RTE_PTYPE_INNER_L4_TCP,
|
||||
/* All others reserved */
|
||||
};
|
||||
cqrd_flags &= CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT
|
||||
| CQ_ENET_RQ_DESC_FLAGS_IPV4 | CQ_ENET_RQ_DESC_FLAGS_IPV6
|
||||
| CQ_ENET_RQ_DESC_FLAGS_TCP | CQ_ENET_RQ_DESC_FLAGS_UDP;
|
||||
return cq_type_table[cqrd_flags];
|
||||
return cq_type_table[cqrd_flags + tnl];
|
||||
}
|
||||
|
||||
static inline void
|
||||
@ -200,10 +234,18 @@ enic_cq_rx_to_pkt_flags(struct cq_desc *cqd, struct rte_mbuf *mbuf)
|
||||
uint32_t l4_flags;
|
||||
l4_flags = mbuf->packet_type & RTE_PTYPE_L4_MASK;
|
||||
|
||||
if (enic_cq_rx_desc_ipv4_csum_ok(cqrd))
|
||||
pkt_flags |= PKT_RX_IP_CKSUM_GOOD;
|
||||
else if (mbuf->packet_type & RTE_PTYPE_L3_IPV4)
|
||||
pkt_flags |= PKT_RX_IP_CKSUM_BAD;
|
||||
/*
|
||||
* When overlay offload is enabled, the NIC may
|
||||
* set ipv4_csum_ok=1 if the inner packet is IPv6..
|
||||
* So, explicitly check for IPv4 before checking
|
||||
* ipv4_csum_ok.
|
||||
*/
|
||||
if (mbuf->packet_type & RTE_PTYPE_L3_IPV4) {
|
||||
if (enic_cq_rx_desc_ipv4_csum_ok(cqrd))
|
||||
pkt_flags |= PKT_RX_IP_CKSUM_GOOD;
|
||||
else
|
||||
pkt_flags |= PKT_RX_IP_CKSUM_BAD;
|
||||
}
|
||||
|
||||
if (l4_flags == RTE_PTYPE_L4_UDP ||
|
||||
l4_flags == RTE_PTYPE_L4_TCP) {
|
||||
@ -245,6 +287,7 @@ enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
|
||||
struct vnic_cq *cq;
|
||||
volatile struct cq_desc *cqd_ptr;
|
||||
uint8_t color;
|
||||
uint8_t tnl;
|
||||
uint16_t seg_length;
|
||||
struct rte_mbuf *first_seg = sop_rq->pkt_first_seg;
|
||||
struct rte_mbuf *last_seg = sop_rq->pkt_last_seg;
|
||||
@ -336,10 +379,21 @@ enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* When overlay offload is enabled, CQ.fcoe indicates the
|
||||
* packet is tunnelled.
|
||||
*/
|
||||
tnl = enic->overlay_offload &&
|
||||
(ciflags & CQ_ENET_RQ_DESC_FLAGS_FCOE) != 0;
|
||||
/* cq rx flags are only valid if eop bit is set */
|
||||
first_seg->packet_type = enic_cq_rx_flags_to_pkt_type(&cqd);
|
||||
first_seg->packet_type =
|
||||
enic_cq_rx_flags_to_pkt_type(&cqd, tnl);
|
||||
enic_cq_rx_to_pkt_flags(&cqd, first_seg);
|
||||
|
||||
/* Wipe the outer types set by enic_cq_rx_flags_to_pkt_type() */
|
||||
if (tnl) {
|
||||
first_seg->packet_type &= ~(RTE_PTYPE_L3_MASK |
|
||||
RTE_PTYPE_L4_MASK);
|
||||
}
|
||||
if (unlikely(packet_error)) {
|
||||
rte_pktmbuf_free(first_seg);
|
||||
rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
|
||||
@ -443,9 +497,10 @@ unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint16_t enic_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
uint16_t enic_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
uint16_t nb_pkts)
|
||||
{
|
||||
struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
|
||||
int32_t ret;
|
||||
uint16_t i;
|
||||
uint64_t ol_flags;
|
||||
@ -454,7 +509,7 @@ uint16_t enic_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
for (i = 0; i != nb_pkts; i++) {
|
||||
m = tx_pkts[i];
|
||||
ol_flags = m->ol_flags;
|
||||
if (ol_flags & ENIC_TX_OFFLOAD_NOTSUP_MASK) {
|
||||
if (ol_flags & wq->tx_offload_notsup_mask) {
|
||||
rte_errno = -ENOTSUP;
|
||||
return i;
|
||||
}
|
||||
@ -558,6 +613,11 @@ uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
|
||||
offload_mode = WQ_ENET_OFFLOAD_MODE_TSO;
|
||||
mss = tx_pkt->tso_segsz;
|
||||
/* For tunnel, need the size of outer+inner headers */
|
||||
if (ol_flags & PKT_TX_TUNNEL_MASK) {
|
||||
header_len += tx_pkt->outer_l2_len +
|
||||
tx_pkt->outer_l3_len;
|
||||
}
|
||||
}
|
||||
|
||||
if ((ol_flags & ol_flags_mask) && (header_len == 0)) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user