dma/idxd: create dmadev instances on PCI probe
When a suitable device is found during the PCI probe, create a dmadev instance for each HW queue. HW definitions required are also included. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Signed-off-by: Kevin Laatz <kevin.laatz@intel.com> Reviewed-by: Conor Walsh <conor.walsh@intel.com>
This commit is contained in:
Kevin Laatz
Thomas Monjalon
parent
55dc0f6096
commit
9449330a84
@ -24,4 +24,67 @@ struct idxd_completion {
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uint32_t invalid_flags;
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} __rte_aligned(32);
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/*** Definitions for Intel(R) Data Streaming Accelerator ***/
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#define IDXD_CMD_SHIFT 20
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enum rte_idxd_cmds {
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idxd_enable_dev = 1,
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idxd_disable_dev,
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idxd_drain_all,
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idxd_abort_all,
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idxd_reset_device,
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idxd_enable_wq,
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idxd_disable_wq,
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idxd_drain_wq,
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idxd_abort_wq,
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idxd_reset_wq,
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};
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/* General bar0 registers */
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struct rte_idxd_bar0 {
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uint32_t __rte_cache_aligned version; /* offset 0x00 */
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uint64_t __rte_aligned(0x10) gencap; /* offset 0x10 */
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uint64_t __rte_aligned(0x10) wqcap; /* offset 0x20 */
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uint64_t __rte_aligned(0x10) grpcap; /* offset 0x30 */
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uint64_t __rte_aligned(0x08) engcap; /* offset 0x38 */
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uint64_t __rte_aligned(0x10) opcap; /* offset 0x40 */
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uint64_t __rte_aligned(0x20) offsets[2]; /* offset 0x60 */
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uint32_t __rte_aligned(0x20) gencfg; /* offset 0x80 */
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uint32_t __rte_aligned(0x08) genctrl; /* offset 0x88 */
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uint32_t __rte_aligned(0x10) gensts; /* offset 0x90 */
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uint32_t __rte_aligned(0x08) intcause; /* offset 0x98 */
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uint32_t __rte_aligned(0x10) cmd; /* offset 0xA0 */
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uint32_t __rte_aligned(0x08) cmdstatus; /* offset 0xA8 */
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uint64_t __rte_aligned(0x20) swerror[4]; /* offset 0xC0 */
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};
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/* workqueue config is provided by array of uint32_t. */
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enum rte_idxd_wqcfg {
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wq_size_idx, /* size is in first 32-bit value */
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wq_threshold_idx, /* WQ threshold second 32-bits */
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wq_mode_idx, /* WQ mode and other flags */
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wq_sizes_idx, /* WQ transfer and batch sizes */
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wq_occ_int_idx, /* WQ occupancy interrupt handle */
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wq_occ_limit_idx, /* WQ occupancy limit */
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wq_state_idx, /* WQ state and occupancy state */
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};
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#define WQ_MODE_SHARED 0
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#define WQ_MODE_DEDICATED 1
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#define WQ_PRIORITY_SHIFT 4
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#define WQ_BATCH_SZ_SHIFT 5
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#define WQ_STATE_SHIFT 30
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#define WQ_STATE_MASK 0x3
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struct rte_idxd_grpcfg {
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uint64_t grpwqcfg[4] __rte_cache_aligned; /* 64-byte register set */
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uint64_t grpengcfg; /* offset 32 */
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uint32_t grpflags; /* offset 40 */
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};
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#define GENSTS_DEV_STATE_MASK 0x03
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#define CMDSTATUS_ACTIVE_SHIFT 31
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#define CMDSTATUS_ACTIVE_MASK (1 << 31)
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#define CMDSTATUS_ERR_MASK 0xFF
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#endif
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@ -6,6 +6,7 @@
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#define _IDXD_INTERNAL_H_
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#include <rte_dmadev_pmd.h>
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#include <rte_spinlock.h>
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#include "idxd_hw_defs.h"
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@ -28,6 +29,16 @@ extern int idxd_pmd_logtype;
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#define IDXD_PMD_ERR(fmt, args...) IDXD_PMD_LOG(ERR, fmt, ## args)
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#define IDXD_PMD_WARN(fmt, args...) IDXD_PMD_LOG(WARNING, fmt, ## args)
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struct idxd_pci_common {
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rte_spinlock_t lk;
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uint8_t wq_cfg_sz;
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volatile struct rte_idxd_bar0 *regs;
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volatile uint32_t *wq_regs_base;
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volatile struct rte_idxd_grpcfg *grp_regs;
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volatile void *portals;
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};
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struct idxd_dmadev {
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/* counters to track the batches */
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unsigned short max_batches;
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@ -59,6 +70,8 @@ struct idxd_dmadev {
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struct {
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unsigned int dsa_id;
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} bus;
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struct idxd_pci_common *pci;
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} u;
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};
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@ -3,6 +3,9 @@
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*/
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#include <rte_bus_pci.h>
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#include <rte_devargs.h>
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#include <rte_dmadev_pmd.h>
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#include <rte_malloc.h>
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#include "idxd_internal.h"
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@ -16,28 +19,290 @@ const struct rte_pci_id pci_id_idxd_map[] = {
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{ .vendor_id = 0, /* sentinel */ },
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};
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static inline int
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idxd_pci_dev_command(struct idxd_dmadev *idxd, enum rte_idxd_cmds command)
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{
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uint8_t err_code;
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uint16_t qid = idxd->qid;
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int i = 0;
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if (command >= idxd_disable_wq && command <= idxd_reset_wq)
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qid = (1 << qid);
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rte_spinlock_lock(&idxd->u.pci->lk);
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idxd->u.pci->regs->cmd = (command << IDXD_CMD_SHIFT) | qid;
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do {
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rte_pause();
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err_code = idxd->u.pci->regs->cmdstatus;
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if (++i >= 1000) {
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IDXD_PMD_ERR("Timeout waiting for command response from HW");
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rte_spinlock_unlock(&idxd->u.pci->lk);
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return err_code;
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}
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} while (err_code & CMDSTATUS_ACTIVE_MASK);
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rte_spinlock_unlock(&idxd->u.pci->lk);
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err_code &= CMDSTATUS_ERR_MASK;
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return -err_code;
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}
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static uint32_t *
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idxd_get_wq_cfg(struct idxd_pci_common *pci, uint8_t wq_idx)
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{
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return RTE_PTR_ADD(pci->wq_regs_base,
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(uintptr_t)wq_idx << (5 + pci->wq_cfg_sz));
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}
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static int
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idxd_is_wq_enabled(struct idxd_dmadev *idxd)
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{
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uint32_t state = idxd_get_wq_cfg(idxd->u.pci, idxd->qid)[wq_state_idx];
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return ((state >> WQ_STATE_SHIFT) & WQ_STATE_MASK) == 0x1;
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}
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static int
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idxd_pci_dev_close(struct rte_dma_dev *dev)
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{
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struct idxd_dmadev *idxd = dev->fp_obj->dev_private;
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uint8_t err_code;
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/* disable the device */
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err_code = idxd_pci_dev_command(idxd, idxd_disable_dev);
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if (err_code) {
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IDXD_PMD_ERR("Error disabling device: code %#x", err_code);
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return err_code;
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}
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IDXD_PMD_DEBUG("IDXD Device disabled OK");
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/* free device memory */
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IDXD_PMD_DEBUG("Freeing device driver memory");
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rte_free(idxd->batch_idx_ring);
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return 0;
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}
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static const struct rte_dma_dev_ops idxd_pci_ops = {
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.dev_close = idxd_pci_dev_close,
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};
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/* each portal uses 4 x 4k pages */
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#define IDXD_PORTAL_SIZE (4096 * 4)
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static int
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init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd,
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unsigned int max_queues)
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{
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struct idxd_pci_common *pci;
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uint8_t nb_groups, nb_engines, nb_wqs;
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uint16_t grp_offset, wq_offset; /* how far into bar0 the regs are */
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uint16_t wq_size, total_wq_size;
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uint8_t lg2_max_batch, lg2_max_copy_size;
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unsigned int i, err_code;
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pci = malloc(sizeof(*pci));
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if (pci == NULL) {
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IDXD_PMD_ERR("%s: Can't allocate memory", __func__);
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err_code = -1;
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goto err;
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}
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rte_spinlock_init(&pci->lk);
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/* assign the bar registers, and then configure device */
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pci->regs = dev->mem_resource[0].addr;
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grp_offset = (uint16_t)pci->regs->offsets[0];
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pci->grp_regs = RTE_PTR_ADD(pci->regs, grp_offset * 0x100);
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wq_offset = (uint16_t)(pci->regs->offsets[0] >> 16);
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pci->wq_regs_base = RTE_PTR_ADD(pci->regs, wq_offset * 0x100);
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pci->portals = dev->mem_resource[2].addr;
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pci->wq_cfg_sz = (pci->regs->wqcap >> 24) & 0x0F;
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/* sanity check device status */
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if (pci->regs->gensts & GENSTS_DEV_STATE_MASK) {
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/* need function-level-reset (FLR) or is enabled */
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IDXD_PMD_ERR("Device status is not disabled, cannot init");
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err_code = -1;
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goto err;
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}
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if (pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK) {
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/* command in progress */
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IDXD_PMD_ERR("Device has a command in progress, cannot init");
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err_code = -1;
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goto err;
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}
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/* read basic info about the hardware for use when configuring */
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nb_groups = (uint8_t)pci->regs->grpcap;
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nb_engines = (uint8_t)pci->regs->engcap;
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nb_wqs = (uint8_t)(pci->regs->wqcap >> 16);
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total_wq_size = (uint16_t)pci->regs->wqcap;
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lg2_max_copy_size = (uint8_t)(pci->regs->gencap >> 16) & 0x1F;
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lg2_max_batch = (uint8_t)(pci->regs->gencap >> 21) & 0x0F;
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IDXD_PMD_DEBUG("nb_groups = %u, nb_engines = %u, nb_wqs = %u",
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nb_groups, nb_engines, nb_wqs);
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/* zero out any old config */
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for (i = 0; i < nb_groups; i++) {
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pci->grp_regs[i].grpengcfg = 0;
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pci->grp_regs[i].grpwqcfg[0] = 0;
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}
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for (i = 0; i < nb_wqs; i++)
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idxd_get_wq_cfg(pci, i)[0] = 0;
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/* limit queues if necessary */
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if (max_queues != 0 && nb_wqs > max_queues) {
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nb_wqs = max_queues;
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if (nb_engines > max_queues)
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nb_engines = max_queues;
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if (nb_groups > max_queues)
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nb_engines = max_queues;
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IDXD_PMD_DEBUG("Limiting queues to %u", nb_wqs);
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}
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/* put each engine into a separate group to avoid reordering */
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if (nb_groups > nb_engines)
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nb_groups = nb_engines;
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if (nb_groups < nb_engines)
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nb_engines = nb_groups;
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/* assign engines to groups, round-robin style */
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for (i = 0; i < nb_engines; i++) {
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IDXD_PMD_DEBUG("Assigning engine %u to group %u",
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i, i % nb_groups);
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pci->grp_regs[i % nb_groups].grpengcfg |= (1ULL << i);
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}
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/* now do the same for queues and give work slots to each queue */
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wq_size = total_wq_size / nb_wqs;
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IDXD_PMD_DEBUG("Work queue size = %u, max batch = 2^%u, max copy = 2^%u",
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wq_size, lg2_max_batch, lg2_max_copy_size);
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for (i = 0; i < nb_wqs; i++) {
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/* add engine "i" to a group */
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IDXD_PMD_DEBUG("Assigning work queue %u to group %u",
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i, i % nb_groups);
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pci->grp_regs[i % nb_groups].grpwqcfg[0] |= (1ULL << i);
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/* now configure it, in terms of size, max batch, mode */
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idxd_get_wq_cfg(pci, i)[wq_size_idx] = wq_size;
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idxd_get_wq_cfg(pci, i)[wq_mode_idx] = (1 << WQ_PRIORITY_SHIFT) |
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WQ_MODE_DEDICATED;
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idxd_get_wq_cfg(pci, i)[wq_sizes_idx] = lg2_max_copy_size |
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(lg2_max_batch << WQ_BATCH_SZ_SHIFT);
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}
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/* dump the group configuration to output */
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for (i = 0; i < nb_groups; i++) {
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IDXD_PMD_DEBUG("## Group %d", i);
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IDXD_PMD_DEBUG(" GRPWQCFG: %"PRIx64, pci->grp_regs[i].grpwqcfg[0]);
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IDXD_PMD_DEBUG(" GRPENGCFG: %"PRIx64, pci->grp_regs[i].grpengcfg);
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IDXD_PMD_DEBUG(" GRPFLAGS: %"PRIx32, pci->grp_regs[i].grpflags);
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}
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idxd->u.pci = pci;
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idxd->max_batches = wq_size;
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/* enable the device itself */
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err_code = idxd_pci_dev_command(idxd, idxd_enable_dev);
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if (err_code) {
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IDXD_PMD_ERR("Error enabling device: code %#x", err_code);
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goto err;
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}
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IDXD_PMD_DEBUG("IDXD Device enabled OK");
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return nb_wqs;
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err:
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free(pci);
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return err_code;
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}
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static int
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idxd_dmadev_probe_pci(struct rte_pci_driver *drv, struct rte_pci_device *dev)
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{
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int ret = 0;
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struct idxd_dmadev idxd = {0};
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uint8_t nb_wqs;
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int qid, ret = 0;
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char name[PCI_PRI_STR_SIZE];
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unsigned int max_queues = 0;
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rte_pci_device_name(&dev->addr, name, sizeof(name));
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IDXD_PMD_INFO("Init %s on NUMA node %d", name, dev->device.numa_node);
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dev->device.driver = &drv->driver;
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if (dev->device.devargs && dev->device.devargs->args[0] != '\0') {
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/* if the number of devargs grows beyond just 1, use rte_kvargs */
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if (sscanf(dev->device.devargs->args,
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"max_queues=%u", &max_queues) != 1) {
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IDXD_PMD_ERR("Invalid device parameter: '%s'",
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dev->device.devargs->args);
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return -1;
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}
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}
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ret = init_pci_device(dev, &idxd, max_queues);
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if (ret < 0) {
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IDXD_PMD_ERR("Error initializing PCI hardware");
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return ret;
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}
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if (idxd.u.pci->portals == NULL) {
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IDXD_PMD_ERR("Error, invalid portal assigned during initialization\n");
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free(idxd.u.pci);
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return -EINVAL;
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}
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nb_wqs = (uint8_t)ret;
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/* set up one device for each queue */
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for (qid = 0; qid < nb_wqs; qid++) {
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char qname[32];
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/* add the queue number to each device name */
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snprintf(qname, sizeof(qname), "%s-q%d", name, qid);
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idxd.qid = qid;
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idxd.portal = RTE_PTR_ADD(idxd.u.pci->portals,
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qid * IDXD_PORTAL_SIZE);
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if (idxd_is_wq_enabled(&idxd))
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IDXD_PMD_ERR("Error, WQ %u seems enabled", qid);
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ret = idxd_dmadev_create(qname, &dev->device,
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&idxd, &idxd_pci_ops);
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if (ret != 0) {
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IDXD_PMD_ERR("Failed to create dmadev %s", name);
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if (qid == 0) /* if no devices using this, free pci */
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free(idxd.u.pci);
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return ret;
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}
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}
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return 0;
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}
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static int
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idxd_dmadev_destroy(const char *name)
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{
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int ret = 0;
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/* rte_dma_close is called by pmd_release */
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ret = rte_dma_pmd_release(name);
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if (ret)
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IDXD_PMD_DEBUG("Device cleanup failed");
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return ret;
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}
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static int
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idxd_dmadev_remove_pci(struct rte_pci_device *dev)
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{
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int i = 0;
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char name[PCI_PRI_STR_SIZE];
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rte_pci_device_name(&dev->addr, name, sizeof(name));
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IDXD_PMD_INFO("Closing %s on NUMA node %d",
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name, dev->device.numa_node);
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IDXD_PMD_INFO("Closing %s on NUMA node %d", name, dev->device.numa_node);
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RTE_DMA_FOREACH_DEV(i) {
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struct rte_dma_info *info = {0};
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rte_dma_info_get(i, info);
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if (strncmp(name, info->dev_name, strlen(name)) == 0)
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idxd_dmadev_destroy(info->dev_name);
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}
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return 0;
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}
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