net/enic: report ring limits and preferred default values
Report min/max ring sizes, alignments, and so on, and rely on the common checks implemented in the rte_ethdev layer. Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com> Reviewed-by: John Daley <johndale@cisco.com>
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@ -482,6 +482,30 @@ static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
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device_info->reta_size = enic->reta_size;
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device_info->hash_key_size = enic->hash_key_size;
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device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads;
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device_info->rx_desc_lim = (struct rte_eth_desc_lim) {
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.nb_max = enic->config.rq_desc_count,
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.nb_min = ENIC_MIN_RQ_DESCS,
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.nb_align = ENIC_ALIGN_DESCS,
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};
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device_info->tx_desc_lim = (struct rte_eth_desc_lim) {
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.nb_max = enic->config.wq_desc_count,
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.nb_min = ENIC_MIN_WQ_DESCS,
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.nb_align = ENIC_ALIGN_DESCS,
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.nb_seg_max = ENIC_TX_XMIT_MAX,
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.nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC,
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};
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device_info->default_rxportconf = (struct rte_eth_dev_portconf) {
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.burst_size = ENIC_DEFAULT_RX_BURST,
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.ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max,
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ENIC_DEFAULT_RX_RING_SIZE),
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.nb_queues = ENIC_DEFAULT_RX_RINGS,
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};
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device_info->default_txportconf = (struct rte_eth_dev_portconf) {
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.burst_size = ENIC_DEFAULT_TX_BURST,
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.ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max,
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ENIC_DEFAULT_TX_RING_SIZE),
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.nb_queues = ENIC_DEFAULT_TX_RINGS,
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};
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}
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static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev)
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@ -743,8 +743,8 @@ int enic_alloc_rq(struct enic *enic, uint16_t queue_idx,
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}
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/* number of descriptors have to be a multiple of 32 */
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nb_sop_desc = (nb_desc / mbufs_per_pkt) & ~0x1F;
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nb_data_desc = (nb_desc - nb_sop_desc) & ~0x1F;
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nb_sop_desc = (nb_desc / mbufs_per_pkt) & ENIC_ALIGN_DESCS_MASK;
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nb_data_desc = (nb_desc - nb_sop_desc) & ENIC_ALIGN_DESCS_MASK;
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rq_sop->max_mbufs_per_pkt = mbufs_per_pkt;
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rq_data->max_mbufs_per_pkt = mbufs_per_pkt;
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@ -752,7 +752,7 @@ int enic_alloc_rq(struct enic *enic, uint16_t queue_idx,
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if (mbufs_per_pkt > 1) {
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min_sop = 64;
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max_sop = ((enic->config.rq_desc_count /
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(mbufs_per_pkt - 1)) & ~0x1F);
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(mbufs_per_pkt - 1)) & ENIC_ALIGN_DESCS_MASK);
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min_data = min_sop * (mbufs_per_pkt - 1);
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max_data = enic->config.rq_desc_count;
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} else {
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@ -870,19 +870,11 @@ int enic_alloc_wq(struct enic *enic, uint16_t queue_idx,
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static int instance;
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wq->socket_id = socket_id;
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if (nb_desc > enic->config.wq_desc_count) {
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dev_warning(enic,
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"WQ %d - number of tx desc in cmd line (%d) "
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"is greater than that in the UCSM/CIMC adapter "
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"policy. Applying the value in the adapter "
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"policy (%d)\n",
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queue_idx, nb_desc, enic->config.wq_desc_count);
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nb_desc = enic->config.wq_desc_count;
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} else if (nb_desc != enic->config.wq_desc_count) {
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dev_info(enic,
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"TX Queues - effective number of descs:%d\n",
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nb_desc);
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}
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/*
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* rte_eth_tx_queue_setup() checks min, max, and alignment. So just
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* print an info message for diagnostics.
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*/
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dev_info(enic, "TX Queues - effective number of descs:%d\n", nb_desc);
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/* Allocate queue resources */
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err = vnic_wq_alloc(enic->vdev, &enic->wq[queue_idx], queue_idx,
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@ -16,6 +16,10 @@
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#define ENIC_MIN_RQ_DESCS 64
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#define ENIC_MAX_RQ_DESCS 4096
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/* A descriptor ring has a multiple of 32 descriptors */
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#define ENIC_ALIGN_DESCS 32
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#define ENIC_ALIGN_DESCS_MASK ~(ENIC_ALIGN_DESCS - 1)
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#define ENIC_MIN_MTU 68
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/* Does not include (possible) inserted VLAN tag and FCS */
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@ -31,6 +35,14 @@
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#define ENIC_DEFAULT_RX_FREE_THRESH 32
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#define ENIC_TX_XMIT_MAX 64
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/* Defaults for dev_info.default_{rx,tx}portconf */
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#define ENIC_DEFAULT_RX_BURST 32
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#define ENIC_DEFAULT_RX_RINGS 1
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#define ENIC_DEFAULT_RX_RING_SIZE 512
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#define ENIC_DEFAULT_TX_BURST 32
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#define ENIC_DEFAULT_TX_RINGS 1
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#define ENIC_DEFAULT_TX_RING_SIZE 512
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#define ENIC_RSS_DEFAULT_CPU 0
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#define ENIC_RSS_BASE_CPU 0
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#define ENIC_RSS_HASH_BITS 7
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