i40e/base: wrap the register definitions for PF and VF
There were quite a few issues when the wrong defines were getting used in the VF driver. This patch defines a new #define PF_DRIVER. All the PF specific register definitions are wrapped in it. The drivers will have to be updated to use the define in the PF driver builds. Makes for a very short register.h for VF drivers. Also fixes the code where PF driver register fields were getting used for VF driver. Signed-off-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Tested-by: Huilong Xu <huilongx.xu@intel.com>
This commit is contained in:
Jingjing Wu
Thomas Monjalon
parent
b28c67c3ba
commit
9783eb15eb
@ -69,6 +69,7 @@ STATIC void i40e_adminq_init_regs(struct i40e_hw *hw)
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hw->aq.arq.len = I40E_VF_ARQLEN1;
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hw->aq.arq.bal = I40E_VF_ARQBAL1;
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hw->aq.arq.bah = I40E_VF_ARQBAH1;
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#ifdef PF_DRIVER
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} else {
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hw->aq.asq.tail = I40E_PF_ATQT;
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hw->aq.asq.head = I40E_PF_ATQH;
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@ -80,6 +81,7 @@ STATIC void i40e_adminq_init_regs(struct i40e_hw *hw)
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hw->aq.arq.len = I40E_PF_ARQLEN;
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hw->aq.arq.bal = I40E_PF_ARQBAL;
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hw->aq.arq.bah = I40E_PF_ARQBAH;
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#endif
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}
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}
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@ -316,8 +318,26 @@ STATIC enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw)
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wr32(hw, hw->aq.asq.tail, 0);
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/* set starting point */
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#ifdef PF_DRIVER
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#ifdef INTEGRATED_VF
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if (!i40e_is_vf(hw))
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wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
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I40E_PF_ATQLEN_ATQENABLE_MASK));
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#else
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wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
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I40E_PF_ATQLEN_ATQENABLE_MASK));
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#endif /* INTEGRATED_VF */
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#endif /* PF_DRIVER */
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#ifdef VF_DRIVER
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#ifdef INTEGRATED_VF
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if (i40e_is_vf(hw))
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wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
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I40E_VF_ATQLEN1_ATQENABLE_MASK));
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#else
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wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
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I40E_VF_ATQLEN1_ATQENABLE_MASK));
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#endif /* INTEGRATED_VF */
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#endif /* VF_DRIVER */
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wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
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wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
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@ -345,8 +365,26 @@ STATIC enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw)
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wr32(hw, hw->aq.arq.tail, 0);
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/* set starting point */
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#ifdef PF_DRIVER
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#ifdef INTEGRATED_VF
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if (!i40e_is_vf(hw))
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wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
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I40E_PF_ARQLEN_ARQENABLE_MASK));
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#else
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wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
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I40E_PF_ARQLEN_ARQENABLE_MASK));
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#endif /* INTEGRATED_VF */
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#endif /* PF_DRIVER */
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#ifdef VF_DRIVER
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#ifdef INTEGRATED_VF
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if (i40e_is_vf(hw))
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wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
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I40E_VF_ARQLEN1_ARQENABLE_MASK));
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#else
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wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
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I40E_VF_ARQLEN1_ARQENABLE_MASK));
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#endif /* INTEGRATED_VF */
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#endif /* VF_DRIVER */
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wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
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wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
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@ -998,7 +1036,22 @@ enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
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i40e_acquire_spinlock(&hw->aq.arq_spinlock);
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/* set next_to_use to head */
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#ifdef PF_DRIVER
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#ifdef INTEGRATED_VF
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if (!i40e_is_vf(hw))
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ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
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#else
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ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
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#endif /* INTEGRATED_VF */
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#endif /* PF_DRIVER */
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#ifdef VF_DRIVER
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#ifdef INTEGRATED_VF
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if (i40e_is_vf(hw))
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ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK);
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#else
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ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK);
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#endif /* INTEGRATED_VF */
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#endif /* VF_DRIVER */
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if (ntu == ntc) {
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/* nothing to do - shouldn't need to update ring's values */
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ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
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@ -1093,9 +1146,6 @@ void i40e_resume_aq(struct i40e_hw *hw)
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hw->aq.asq.next_to_use = 0;
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hw->aq.asq.next_to_clean = 0;
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#if (I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK)
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#error I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK
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#endif
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i40e_config_asq_regs(hw);
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hw->aq.arq.next_to_use = 0;
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@ -371,9 +371,27 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
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bool i40e_check_asq_alive(struct i40e_hw *hw)
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{
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if (hw->aq.asq.len)
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return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
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else
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return false;
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#ifdef PF_DRIVER
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#ifdef INTEGRATED_VF
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if (!i40e_is_vf(hw))
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return !!(rd32(hw, hw->aq.asq.len) &
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I40E_PF_ATQLEN_ATQENABLE_MASK);
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#else
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return !!(rd32(hw, hw->aq.asq.len) &
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I40E_PF_ATQLEN_ATQENABLE_MASK);
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#endif /* INTEGRATED_VF */
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#endif /* PF_DRIVER */
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#ifdef VF_DRIVER
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#ifdef INTEGRATED_VF
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if (i40e_is_vf(hw))
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return !!(rd32(hw, hw->aq.asq.len) &
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I40E_VF_ATQLEN1_ATQENABLE_MASK);
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#else
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return !!(rd32(hw, hw->aq.asq.len) &
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I40E_VF_ATQLEN1_ATQENABLE_MASK);
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#endif /* INTEGRATED_VF */
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#endif /* VF_DRIVER */
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return false;
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}
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/**
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@ -35,6 +35,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define _I40E_REGISTER_H_
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#ifdef PF_DRIVER
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#define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */
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#define I40E_GL_ARQBAH_ARQBAH_SHIFT 0
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#define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
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@ -1609,6 +1610,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_MSIX_TVCTRL_MAX_INDEX 128
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#define I40E_MSIX_TVCTRL_MASK_SHIFT 0
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#define I40E_MSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT)
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#endif /* PF_DRIVER */
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#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
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#define I40E_VFMSIX_PBA1_MAX_INDEX 19
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#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
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@ -1631,6 +1633,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639
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#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
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#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
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#ifdef PF_DRIVER
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#define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
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#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0
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#define I40E_GLNVM_FLA_FL_SCK_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT)
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@ -3150,6 +3153,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_PRTPM_SAL_MAX_INDEX 3
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#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0
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#define I40E_PRTPM_SAL_PFPM_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT)
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#endif /* PF_DRIVER */
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#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
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#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0
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#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)
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