ixgbe: cleanups
- Removed the not needed casting. - ixgbe_dev_rx_init(): shorten the lines by defining a local alias variable to access &dev->data->dev_conf.rxmode. Signed-off-by: Vlad Zolotarov <vladz@cloudius-systems.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
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@ -1031,8 +1031,7 @@ ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq)
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int diag, i;
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/* allocate buffers in bulk directly into the S/W ring */
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alloc_idx = (uint16_t)(rxq->rx_free_trigger -
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(rxq->rx_free_thresh - 1));
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alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
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rxep = &rxq->sw_ring[alloc_idx];
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diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
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rxq->rx_free_thresh);
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@ -1060,10 +1059,9 @@ ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq)
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IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
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/* update state of internal queue structure */
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rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
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rxq->rx_free_thresh);
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rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
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if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
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rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
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rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
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/* no errors */
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return 0;
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@ -3590,6 +3588,7 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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uint32_t rxcsum;
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uint16_t buf_size;
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uint16_t i;
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struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
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PMD_INIT_FUNC_TRACE();
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hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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@ -3612,7 +3611,7 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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* Configure CRC stripping, if any.
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*/
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hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
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if (dev->data->dev_conf.rxmode.hw_strip_crc)
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if (rx_conf->hw_strip_crc)
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hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
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else
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hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
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@ -3620,11 +3619,11 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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/*
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* Configure jumbo frame support, if any.
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*/
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if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
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if (rx_conf->jumbo_frame == 1) {
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hlreg0 |= IXGBE_HLREG0_JUMBOEN;
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maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
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maxfrs &= 0x0000FFFF;
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maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
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maxfrs |= (rx_conf->max_rx_pkt_len << 16);
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IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
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} else
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hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
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@ -3648,9 +3647,7 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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* Reset crc_len in case it was changed after queue setup by a
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* call to configure.
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*/
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rxq->crc_len = (uint8_t)
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((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
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ETHER_CRC_LEN);
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rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
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/* Setup the Base and Length of the Rx Descriptor Rings */
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bus_addr = rxq->rx_ring_phys_addr;
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@ -3668,7 +3665,7 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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/*
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* Configure Header Split
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*/
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if (dev->data->dev_conf.rxmode.header_split) {
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if (rx_conf->header_split) {
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if (hw->mac.type == ixgbe_mac_82599EB) {
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/* Must setup the PSRTYPE register */
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uint32_t psrtype;
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@ -3678,7 +3675,7 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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IXGBE_PSRTYPE_IPV6HDR;
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IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
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}
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srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
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srrctl = ((rx_conf->split_hdr_size <<
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IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
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IXGBE_SRRCTL_BSIZEHDR_MASK);
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srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
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@ -3712,7 +3709,7 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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dev->data->scattered_rx = 1;
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}
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if (dev->data->dev_conf.rxmode.enable_scatter)
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if (rx_conf->enable_scatter)
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dev->data->scattered_rx = 1;
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ixgbe_set_rx_function(dev);
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@ -3729,7 +3726,7 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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*/
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rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
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rxcsum |= IXGBE_RXCSUM_PCSD;
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if (dev->data->dev_conf.rxmode.hw_ip_checksum)
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if (rx_conf->hw_ip_checksum)
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rxcsum |= IXGBE_RXCSUM_IPPCSE;
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else
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rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
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@ -3739,7 +3736,7 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev)
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if (hw->mac.type == ixgbe_mac_82599EB ||
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hw->mac.type == ixgbe_mac_X540) {
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rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
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if (dev->data->dev_conf.rxmode.hw_strip_crc)
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if (rx_conf->hw_strip_crc)
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rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
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else
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rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
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