net/mlx5: fix Tx max inline with TSO
When TSO is enabled, Verbs layer aggregates the TSO
inline size with the txq inline size for the Tx creation,
while the PMD takes the maximum among them.
Fixing it by adjusting the max inline parameter before
passing to to Verbs.
Fixes: 3f13f8c23a
("net/mlx5: support hardware TSO")
Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
Acked-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
This commit is contained in:
parent
70fca51612
commit
993b2455fb
@ -230,6 +230,9 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
|
||||
struct ibv_exp_cq_attr cq_attr;
|
||||
} attr;
|
||||
unsigned int cqe_n;
|
||||
const unsigned int max_tso_inline = ((MLX5_MAX_TSO_HEADER +
|
||||
(RTE_CACHE_LINE_SIZE - 1)) /
|
||||
RTE_CACHE_LINE_SIZE);
|
||||
int ret = 0;
|
||||
|
||||
if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
|
||||
@ -307,16 +310,23 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
|
||||
priv->inline_max_packet_sz) +
|
||||
(RTE_CACHE_LINE_SIZE - 1)) /
|
||||
RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
|
||||
} else if (priv->tso) {
|
||||
int inline_diff = tmpl.txq.max_inline - max_tso_inline;
|
||||
|
||||
/*
|
||||
* Adjust inline value as Verbs aggregates
|
||||
* tso_inline and txq_inline fields.
|
||||
*/
|
||||
attr.init.cap.max_inline_data = inline_diff > 0 ?
|
||||
inline_diff *
|
||||
RTE_CACHE_LINE_SIZE :
|
||||
0;
|
||||
} else {
|
||||
attr.init.cap.max_inline_data =
|
||||
tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;
|
||||
}
|
||||
}
|
||||
if (priv->tso) {
|
||||
uint16_t max_tso_inline = ((MLX5_MAX_TSO_HEADER +
|
||||
(RTE_CACHE_LINE_SIZE - 1)) /
|
||||
RTE_CACHE_LINE_SIZE);
|
||||
|
||||
attr.init.max_tso_header =
|
||||
max_tso_inline * RTE_CACHE_LINE_SIZE;
|
||||
attr.init.comp_mask |= IBV_EXP_QP_INIT_ATTR_MAX_TSO_HEADER;
|
||||
|
Loading…
Reference in New Issue
Block a user