net/mlx5: cleanup memory barriers

Updating a consumer index to HW doesn't require a memory barrier in case
that there's no updated data to be posted to HW, but a compiler barrier
is sufficient. rte_wmb() is replaced with rte_io_wmb() when it makes
changes visible to HW, not other core.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
This commit is contained in:
Yongseok Koh 2017-10-09 11:46:54 -07:00 committed by Ferruh Yigit
parent 0887aa7f27
commit 9afa3f7465
3 changed files with 5 additions and 5 deletions

View File

@ -1928,9 +1928,9 @@ skip:
return 0;
/* Update the consumer index. */
rxq->rq_ci = rq_ci >> sges_n;
rte_wmb();
rte_io_wmb();
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
rte_wmb();
rte_io_wmb();
*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
#ifdef MLX5_PMD_SOFT_COUNTERS
/* Increment packets counter. */

View File

@ -504,7 +504,7 @@ mlx5_tx_complete(struct mlx5_txq_data *txq)
txq->cq_ci = cq_ci;
txq->elts_tail = elts_tail;
/* Update the consumer index. */
rte_wmb();
rte_compiler_barrier();
*txq->cq_db = rte_cpu_to_be_32(cq_ci);
}

View File

@ -567,7 +567,7 @@ rxq_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n)
wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
RTE_PKTMBUF_HEADROOM);
rxq->rq_ci += n;
rte_wmb();
rte_io_wmb();
*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
}
@ -1259,7 +1259,7 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
rcvd_pkt += n;
}
}
rte_wmb();
rte_compiler_barrier();
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
return rcvd_pkt;
}