net/mlx5: cleanup memory barriers
Updating a consumer index to HW doesn't require a memory barrier in case that there's no updated data to be posted to HW, but a compiler barrier is sufficient. rte_wmb() is replaced with rte_io_wmb() when it makes changes visible to HW, not other core. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com> Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
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@ -1928,9 +1928,9 @@ skip:
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return 0;
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/* Update the consumer index. */
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rxq->rq_ci = rq_ci >> sges_n;
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rte_wmb();
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rte_io_wmb();
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*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
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rte_wmb();
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rte_io_wmb();
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*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
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#ifdef MLX5_PMD_SOFT_COUNTERS
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/* Increment packets counter. */
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@ -504,7 +504,7 @@ mlx5_tx_complete(struct mlx5_txq_data *txq)
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txq->cq_ci = cq_ci;
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txq->elts_tail = elts_tail;
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/* Update the consumer index. */
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rte_wmb();
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rte_compiler_barrier();
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*txq->cq_db = rte_cpu_to_be_32(cq_ci);
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}
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@ -567,7 +567,7 @@ rxq_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n)
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wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
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RTE_PKTMBUF_HEADROOM);
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rxq->rq_ci += n;
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rte_wmb();
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rte_io_wmb();
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*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
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}
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@ -1259,7 +1259,7 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
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rcvd_pkt += n;
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}
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}
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rte_wmb();
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rte_compiler_barrier();
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*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
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return rcvd_pkt;
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}
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