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net/sfc/base: move Tx config to ef10 NIC board config

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Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
This commit is contained in:
Andy Moreton 2018-02-20 07:34:13 +00:00 committed by Ferruh Yigit
parent 32a3020461
commit 9bd777a7e6
4 changed files with 10 additions and 30 deletions
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10
drivers/net/sfc/base/ef10_nic.c
View File

@ -1645,6 +1645,16 @@ ef10_nic_board_cfg(
*/
encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Maximum number of bytes into the frame the TCP header can start for
* firmware assisted TSO to work.
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)

10
drivers/net/sfc/base/hunt_nic.c
View File

@ -205,10 +205,6 @@ hunt_board_cfg(
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@ -254,12 +250,6 @@ hunt_board_cfg(
encp->enc_intr_vec_base = base;
encp->enc_intr_limit = nvec;
/*
* Maximum number of bytes into the frame the TCP header can start for
* firmware assisted TSO to work.
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
goto fail7;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;

10
drivers/net/sfc/base/medford2_nic.c
View File

@ -137,10 +137,6 @@ medford2_board_cfg(
}
encp->enc_rx_buf_align_end = end_padding;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@ -187,12 +183,6 @@ medford2_board_cfg(
encp->enc_intr_vec_base = base;
encp->enc_intr_limit = nvec;
/*
* Maximum number of bytes into the frame the TCP header can start for
* firmware assisted TSO to work.
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
/*
* Medford2 stores a single global copy of VPD, not per-PF as on
* Huntington.

10
drivers/net/sfc/base/medford_nic.c
View File

@ -136,10 +136,6 @@ medford_board_cfg(
}
encp->enc_rx_buf_align_end = end_padding;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@ -186,12 +182,6 @@ medford_board_cfg(
encp->enc_intr_vec_base = base;
encp->enc_intr_limit = nvec;
/*
* Maximum number of bytes into the frame the TCP header can start for
* firmware assisted TSO to work.
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
/*
* Medford stores a single global copy of VPD, not per-PF as on
* Huntington.