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net/ice: fix ESP flow director with SPI as input set

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FDIR can't work when SPI as inputset for both ESP over IP and ESP
over UDP flow. This patch fixes this issue by adding the corresponding
input set for ESP over IP and ESP over UDP when parsing input set. Also,
it adds input set bit for NAT_T_ESP to distinguish ESP over IP and ESP
over UDP.

Fixes: 70feafc1a3f2 ("net/ice: support ESP/NATT flow director to match outer IP")

Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
This commit is contained in:
Simei Su 2021-07-13 10:10:24 +08:00 committed by Qi Zhang
parent 0a37b22875
commit a02d9d9bae
2 changed files with 13 additions and 4 deletions
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14
drivers/net/ice/ice_fdir_filter.c
View File

@ -100,11 +100,11 @@
#define ICE_FDIR_INSET_IPV4_NATT_ESP (\
ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \
ICE_INSET_ESP_SPI)
ICE_INSET_NAT_T_ESP_SPI)
#define ICE_FDIR_INSET_IPV6_NATT_ESP (\
ICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST | \
ICE_INSET_ESP_SPI)
ICE_INSET_NAT_T_ESP_SPI)
static struct ice_pattern_match_item ice_fdir_pattern_list[] = {
{pattern_ethertype, ICE_FDIR_INSET_ETH, ICE_INSET_NONE, ICE_INSET_NONE},
@ -951,6 +951,8 @@ ice_fdir_input_set_parse(uint64_t inset, enum ice_flow_field *field)
{ICE_INSET_GTPU_TEID, ICE_FLOW_FIELD_IDX_GTPU_IP_TEID},
{ICE_INSET_GTPU_QFI, ICE_FLOW_FIELD_IDX_GTPU_EH_QFI},
{ICE_INSET_VXLAN_VNI, ICE_FLOW_FIELD_IDX_VXLAN_VNI},
{ICE_INSET_ESP_SPI, ICE_FLOW_FIELD_IDX_ESP_SPI},
{ICE_INSET_NAT_T_ESP_SPI, ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI},
};
for (i = 0, j = 0; i < RTE_DIM(ice_inset_map); i++) {
@ -2128,8 +2130,12 @@ ice_fdir_parse_pattern(__rte_unused struct ice_adapter *ad,
if (!(esp_spec && esp_mask))
break;
if (esp_mask->hdr.spi == UINT32_MAX)
*input_set |= ICE_INSET_ESP_SPI;
if (esp_mask->hdr.spi == UINT32_MAX) {
if (l4 == RTE_FLOW_ITEM_TYPE_UDP)
*input_set |= ICE_INSET_NAT_T_ESP_SPI;
else
*input_set |= ICE_INSET_ESP_SPI;
}
if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
filter->input.ip.v4.sec_parm_idx =

3
drivers/net/ice/ice_generic_flow.h
View File

@ -26,6 +26,7 @@
#define ICE_PROT_AH BIT_ULL(15)
#define ICE_PROT_L2TPV3OIP BIT_ULL(16)
#define ICE_PROT_PFCP BIT_ULL(17)
#define ICE_PROT_NAT_T_ESP BIT_ULL(18)
/* field */
@ -117,6 +118,8 @@
(ICE_PROT_PFCP | ICE_PFCP_S_FIELD)
#define ICE_INSET_PFCP_SEID \
(ICE_PROT_PFCP | ICE_PFCP_S_FIELD | ICE_PFCP_SEID)
#define ICE_INSET_NAT_T_ESP_SPI \
(ICE_PROT_NAT_T_ESP | ICE_ESP_SPI)
/* empty pattern */
extern enum rte_flow_item_type pattern_empty[];