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net/bnxt: identify duplicate flows

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Conflict resolution feature allows rejection of flows based on
the previously added flows that conflict. For instance, a five
tuple flow is added and then you add a new flow with only 4 tuple
instead having same layer2 details then it will be rejected.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
This commit is contained in:
Kishore Padmanabha 2021-05-30 14:29:05 +05:30 committed by Ajit Khaparde
parent 9cbfa4cfd5
commit a241760189
29 changed files with 16243 additions and 59887 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
devtools/parse-flow-support.sh
View File

@ -22,7 +22,7 @@ exclude() # <pattern>
case $(basename $dir) in
bnxt)
filter=$(sed -n "/$1/{N;/TYPE_NOT_SUPPORTED/P;}" \
$dir/tf_ulp/ulp_template_db{,_tbl}.c |
$dir/tf_ulp/ulp_rte_handler_tbl.c |
grep -wo "$1[[:alnum:]_]*" | sort -u |
tr '\n' '|' | sed 's,.$,\n,')
grep -vE "$filter";;

10
doc/guides/nics/features/bnxt.ini
View File

@ -67,12 +67,22 @@ vxlan = Y
[rte_flow actions]
count = Y
dec_ttl = Y
drop = Y
jump = Y
mark = Y
of_pop_vlan = Y
of_push_vlan = Y
of_set_vlan_pcp = Y
of_set_vlan_vid = Y
pf = Y
phy_port = Y
port_id = Y
rss = Y
set_ipv4_dst = Y
set_ipv4_src = Y
set_tp_dst = Y
set_tp_src = Y
vf = Y
vxlan_decap = Y
vxlan_encap = Y

12
drivers/net/bnxt/tf_ulp/bnxt_ulp.c
View File

@ -22,7 +22,6 @@
#include "ulp_flow_db.h"
#include "ulp_mapper.h"
#include "ulp_port_db.h"
#include "ulp_tun.h"
/* Linked list of all TF sessions. */
STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list =
@ -55,14 +54,13 @@ bnxt_ulp_devid_get(struct bnxt *bp,
{
if (BNXT_CHIP_P5(bp))
return -EINVAL;
/* Assuming Whitney */
*ulp_dev_id = BNXT_ULP_DEVICE_ID_WH_PLUS;
if (BNXT_STINGRAY(bp))
*ulp_dev_id = BNXT_ULP_DEVICE_ID_STINGRAY;
else
/* Assuming Whitney */
*ulp_dev_id = BNXT_ULP_DEVICE_ID_WH_PLUS;
return 0;
}
@ -400,21 +398,18 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
if (bnxt_ulp_cntxt_mem_type_get(bp->ulp_ctx, &mtype))
return -EINVAL;
if (mtype != BNXT_ULP_FLOW_MEM_TYPE_EXT) {
BNXT_TF_DBG(INFO, "Table Scope alloc is not required\n");
return 0;
}
bnxt_init_tbl_scope_parms(bp, &params);
rc = tf_alloc_tbl_scope(&bp->tfp, &params);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to allocate eem table scope rc = %d\n",
rc);
return rc;
}
rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set table scope id\n");
@ -534,8 +529,6 @@ ulp_ctx_init(struct bnxt *bp,
if (rc)
goto error_deinit;
ulp_tun_tbl_init(ulp_data->tun_tbl);
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
return rc;
@ -547,8 +540,7 @@ error_deinit:
/* The function to initialize ulp dparms with devargs */
static int32_t
ulp_dparms_init(struct bnxt *bp,
struct bnxt_ulp_context *ulp_ctx)
ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
{
struct bnxt_ulp_device_params *dparms;
uint32_t dev_id;

8
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
View File

@ -79,7 +79,6 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
struct ulp_rte_parser_params *params,
enum bnxt_ulp_fdb_type flow_type)
{
memset(mapper_cparms, 0, sizeof(*mapper_cparms));
mapper_cparms->flow_type = flow_type;
mapper_cparms->app_priority = params->priority;
mapper_cparms->dir_attr = params->dir_attr;
@ -95,6 +94,12 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->parent_flow = params->parent_flow;
mapper_cparms->parent_fid = params->parent_fid;
mapper_cparms->fld_bitmap = &params->fld_bitmap;
/* update the signature fields into the computed field list */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,
params->hdr_sig_id);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID,
params->flow_sig_id);
}
/* Function to create the rte flow. */
@ -177,7 +182,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
params.fid = fid;
params.func_id = func_id;
params.priority = attr->priority;
params.port_id = dev->data->port_id;
/* Perform the rte flow post process */
ret = bnxt_ulp_rte_parser_post_process(&params);
if (ret == BNXT_TF_RC_ERROR)

1
drivers/net/bnxt/tf_ulp/meson.build
View File

@ -23,6 +23,7 @@ sources += files(
'ulp_fc_mgr.c',
'ulp_tun.c',
'ulp_gen_tbl.c',
'ulp_rte_handler_tbl.c',
'ulp_template_db_wh_plus_act.c',
'ulp_template_db_wh_plus_class.c',
'ulp_template_db_stingray_act.c',

10
drivers/net/bnxt/tf_ulp/ulp_def_rules.c
View File

@ -366,7 +366,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
goto err1;
}
rc = ulp_flow_db_fid_alloc(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT,
rc = ulp_flow_db_fid_alloc(ulp_ctx, mapper_params.flow_type,
mapper_params.func_id, &fid);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
@ -383,7 +383,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
return 0;
err3:
ulp_flow_db_fid_free(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT, fid);
ulp_flow_db_fid_free(ulp_ctx, mapper_params.flow_type, fid);
err2:
bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
err1:
@ -437,7 +437,7 @@ void
bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global)
{
struct bnxt_ulp_df_rule_info *info;
uint16_t port_id;
uint8_t port_id;
if (!BNXT_TRUFLOW_EN(bp) ||
BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev))
@ -501,7 +501,7 @@ int32_t
bnxt_ulp_create_df_rules(struct bnxt *bp)
{
struct bnxt_ulp_df_rule_info *info;
uint16_t port_id;
uint8_t port_id;
int rc;
if (!BNXT_TRUFLOW_EN(bp) ||
@ -575,7 +575,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev)
struct rte_eth_dev *parent_dev = vfr->parent_dev;
struct bnxt *bp = parent_dev->data->dev_private;
uint16_t vfr_port_id = vfr_ethdev->data->port_id;
uint16_t port_id;
uint8_t port_id;
int rc;
if (!bp || !BNXT_TRUFLOW_EN(bp))

62
drivers/net/bnxt/tf_ulp/ulp_flow_db.c
View File

@ -48,17 +48,21 @@ ulp_flow_db_active_flows_bit_set(struct bnxt_ulp_flow_db *flow_db,
uint32_t a_idx = idx / ULP_INDEX_BITMAP_SIZE;
if (flag) {
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type ==
BNXT_ULP_FDB_TYPE_RID)
ULP_INDEX_BITMAP_SET(f_tbl->active_reg_flows[a_idx],
idx);
else
if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type ==
BNXT_ULP_FDB_TYPE_RID)
ULP_INDEX_BITMAP_SET(f_tbl->active_dflt_flows[a_idx],
idx);
} else {
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type ==
BNXT_ULP_FDB_TYPE_RID)
ULP_INDEX_BITMAP_RESET(f_tbl->active_reg_flows[a_idx],
idx);
else
if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type ==
BNXT_ULP_FDB_TYPE_RID)
ULP_INDEX_BITMAP_RESET(f_tbl->active_dflt_flows[a_idx],
idx);
}
@ -85,9 +89,15 @@ ulp_flow_db_active_flows_bit_is_set(struct bnxt_ulp_flow_db *flow_db,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
return ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],
idx);
else
else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT)
return ULP_INDEX_BITMAP_GET(f_tbl->active_dflt_flows[a_idx],
idx);
else if (flow_type == BNXT_ULP_FDB_TYPE_RID)
return (ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],
idx) &&
ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],
idx));
return 0;
}
static inline enum tf_dir
@ -213,7 +223,7 @@ ulp_flow_db_alloc_resource(struct bnxt_ulp_flow_db *flow_db)
return -ENOMEM;
}
size = (flow_tbl->num_flows / sizeof(uint64_t)) + 1;
size = ULP_BYTE_ROUND_OFF_8(size);
size = ULP_BYTE_ROUND_OFF_8(size);
flow_tbl->active_reg_flows = rte_zmalloc("active reg flows", size,
ULP_BUFFER_ALIGN_64_BYTE);
if (!flow_tbl->active_reg_flows) {
@ -617,7 +627,7 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt,
return -EINVAL;
}
if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
BNXT_TF_DBG(ERR, "Invalid flow type\n");
return -EINVAL;
}
@ -674,7 +684,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
return -EINVAL;
}
if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
BNXT_TF_DBG(ERR, "Invalid flow type\n");
return -EINVAL;
}
@ -688,7 +698,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
/* check if the flow is active or not */
if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {
BNXT_TF_DBG(ERR, "flow does not exist\n");
BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid);
return -EINVAL;
}
@ -769,7 +779,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
return -EINVAL;
}
if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
BNXT_TF_DBG(ERR, "Invalid flow type\n");
return -EINVAL;
}
@ -783,7 +793,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
/* check if the flow is active or not */
if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {
BNXT_TF_DBG(ERR, "flow does not exist\n");
BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid);
return -EINVAL;
}
@ -868,9 +878,8 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
enum bnxt_ulp_fdb_type flow_type,
uint32_t fid)
{
struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_tbl *flow_tbl;
struct bnxt_ulp_flow_db *flow_db;
struct bnxt_ulp_flow_tbl *flow_tbl;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
@ -878,7 +887,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
return -EINVAL;
}
if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
BNXT_TF_DBG(ERR, "Invalid flow type\n");
return -EINVAL;
}
@ -893,7 +902,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
/* check if the flow is active or not */
if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {
BNXT_TF_DBG(ERR, "flow does not exist\n");
BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid);
return -EINVAL;
}
flow_tbl->head_index--;
@ -901,6 +910,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
BNXT_TF_DBG(ERR, "FlowDB: Head Ptr is zero\n");
return -ENOENT;
}
flow_tbl->flow_tbl_stack[flow_tbl->head_index] = fid;
/* Clear the flows bitmap */
@ -909,18 +919,12 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, fid, 0);
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
if (!tun_tbl)
return -EINVAL;
ulp_clear_tun_inner_entry(tun_tbl, fid);
/* all good, return success */
return 0;
}
/*
* Get the flow database entry details
*Get the flow database entry details
*
* ulp_ctxt [in] Ptr to ulp_context
* flow_type [in] - specify default or regular
@ -947,7 +951,7 @@ ulp_flow_db_resource_get(struct bnxt_ulp_context *ulp_ctxt,
return -EINVAL;
}
if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
BNXT_TF_DBG(ERR, "Invalid flow type\n");
return -EINVAL;
}
@ -1003,10 +1007,14 @@ ulp_flow_db_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
uint64_t *active_flows;
struct bnxt_ulp_flow_tbl *flowtbl = &flow_db->flow_tbl;
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) {
active_flows = flowtbl->active_reg_flows;
else
} else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT) {
active_flows = flowtbl->active_dflt_flows;
} else {
BNXT_TF_DBG(ERR, "Invalid flow type %x\n", flow_type);
return -EINVAL;
}
do {
/* increment the flow id to find the next valid flow id */
@ -1199,7 +1207,7 @@ ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx,
return -EINVAL;
}
if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
BNXT_TF_DBG(ERR, "Invalid flow type\n");
return -EINVAL;
}
@ -1601,7 +1609,7 @@ ulp_flow_db_child_flow_reset(struct bnxt_ulp_context *ulp_ctxt,
return -EINVAL;
}
if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
BNXT_TF_DBG(ERR, "Invalid flow type\n");
return -EINVAL;
}

38
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
View File

@ -47,7 +47,7 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data)
if (tbl->result_num_entries != 0) {
/* add 4 bytes for reference count */
entry->mem_data_size = (tbl->result_num_entries + 1) *
(tbl->result_byte_size + sizeof(uint32_t));
(tbl->result_num_bytes + sizeof(uint32_t));
/* allocate the big chunk of memory */
entry->mem_data = rte_zmalloc("ulp mapper gen tbl",
@ -60,7 +60,7 @@ ulp_mapper_generic_tbl_list_init(struct bnxt_ulp_mapper_data *mapper_data)
}
/* Populate the generic table container */
entry->container.num_elem = tbl->result_num_entries;
entry->container.byte_data_size = tbl->result_byte_size;
entry->container.byte_data_size = tbl->result_num_bytes;
entry->container.ref_count =
(uint32_t *)entry->mem_data;
size = sizeof(uint32_t) * (tbl->result_num_entries + 1);
@ -168,7 +168,6 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir)
* Set the data in the generic table entry, Data is in Big endian format
*
* entry [in] - generic table entry
* offset [in] - The offset in bits where the data has to be set
* len [in] - The length of the data in bits to be set
* data [in] - pointer to the data to be used for setting the value.
* data_size [in] - length of the data pointer in bytes.
@ -177,7 +176,7 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir)
*/
int32_t
ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry,
uint32_t offset, uint32_t len, uint8_t *data,
uint32_t len, uint8_t *data,
uint32_t data_size)
{
/* validate the null arguments */
@ -187,32 +186,13 @@ ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry,
}
/* check the size of the buffer for validation */
if ((offset + len) > ULP_BYTE_2_BITS(entry->byte_data_size) ||
if (len > ULP_BYTE_2_BITS(entry->byte_data_size) ||
data_size < ULP_BITS_2_BYTE(len)) {
BNXT_TF_DBG(ERR, "invalid offset or length %x:%x:%x\n",
offset, len, entry->byte_data_size);
BNXT_TF_DBG(ERR, "invalid offset or length %x:%x\n",
len, entry->byte_data_size);
return -EINVAL;
}
/* adjust the data pointer */
data = data + (data_size - ULP_BITS_2_BYTE(len));
/* Push the data into the byte data array */
if (entry->byte_order == BNXT_ULP_BYTE_ORDER_LE) {
if (ulp_bs_push_lsb(entry->byte_data, offset, len, data) !=
len) {
BNXT_TF_DBG(ERR, "write failed offset = %x, len =%x\n",
offset, len);
return -EIO;
}
} else {
if (ulp_bs_push_msb(entry->byte_data, offset, len, data) !=
len) {
BNXT_TF_DBG(ERR, "write failed offset = %x, len =%x\n",
offset, len);
return -EIO;
}
}
memcpy(entry->byte_data, data, ULP_BITS_2_BYTE(len));
return 0;
}
@ -267,7 +247,7 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
{
struct ulp_mapper_gen_tbl_entry entry;
int32_t tbl_idx;
uint32_t fid;
uint32_t fid = 0;
/* Extract the resource sub type and direction */
tbl_idx = ulp_mapper_gen_tbl_idx_calculate(res->resource_sub_type,
@ -310,7 +290,7 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
fid = tfp_be_to_cpu_32(fid);
/* Destroy the flow associated with the shared flow id */
if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_RID,
fid))
BNXT_TF_DBG(ERR, "Error in deleting shared flow id %x\n", fid);

3
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
View File

@ -101,7 +101,6 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir);
* Set the data in the generic table entry
*
* entry [in] - generic table entry
* offset [in] - The offset in bits where the data has to be set
* len [in] - The length of the data in bits to be set
* data [in] - pointer to the data to be used for setting the value.
* data_size [in] - length of the data pointer in bytes.
@ -110,7 +109,7 @@ ulp_mapper_gen_tbl_idx_calculate(uint32_t res_sub_type, uint32_t dir);
*/
int32_t
ulp_mapper_gen_tbl_entry_data_set(struct ulp_mapper_gen_tbl_entry *entry,
uint32_t offset, uint32_t len, uint8_t *data,
uint32_t len, uint8_t *data,
uint32_t data_size);
/*

909
drivers/net/bnxt/tf_ulp/ulp_mapper.c
View File

File diff suppressed because it is too large Load Diff

2
drivers/net/bnxt/tf_ulp/ulp_matcher.c
View File

@ -77,6 +77,8 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
BNXT_TF_DBG(DEBUG, "Found matching pattern template %d\n",
class_match->class_tid);
*class_id = class_match->class_tid;
params->hdr_sig_id = class_match->hdr_sig_id;
params->flow_sig_id = class_match->flow_sig_id;
return BNXT_TF_RC_SUCCESS;
error:

4
drivers/net/bnxt/tf_ulp/ulp_port_db.c
View File

@ -185,15 +185,13 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
port_data = &port_db->phy_port_list[func->phy_port_id];
if (!port_data->port_valid) {
port_data->port_svif =
bnxt_get_svif(port_id, false,
BNXT_ULP_INTF_TYPE_INVALID);
bnxt_get_svif(port_id, false, BNXT_ULP_INTF_TYPE_INVALID);
port_data->port_spif = bnxt_get_phy_port_id(port_id);
port_data->port_parif =
bnxt_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID);
port_data->port_vport = bnxt_get_vport(port_id);
port_data->port_valid = true;
}
return 0;
}

412
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c Normal file
View File

@ -0,0 +1,412 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2021 Broadcom
* All rights reserved.
*/
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "ulp_rte_parser.h"
/*
* This structure has to be indexed based on the rte_flow_action_type that is
* part of DPDK. The below array is list of parsing functions for each of the
* flow actions that are supported.
*/
struct bnxt_ulp_rte_act_info ulp_act_info[] = {
[RTE_FLOW_ACTION_TYPE_END] = {
.act_type = BNXT_ULP_ACT_TYPE_END,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_VOID] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_void_act_handler
},
[RTE_FLOW_ACTION_TYPE_PASSTHRU] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_JUMP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_jump_act_handler
},
[RTE_FLOW_ACTION_TYPE_MARK] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_mark_act_handler
},
[RTE_FLOW_ACTION_TYPE_FLAG] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_QUEUE] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_DROP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_drop_act_handler
},
[RTE_FLOW_ACTION_TYPE_COUNT] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_count_act_handler
},
[RTE_FLOW_ACTION_TYPE_RSS] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_rss_act_handler
},
[RTE_FLOW_ACTION_TYPE_PF] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_pf_act_handler
},
[RTE_FLOW_ACTION_TYPE_VF] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_vf_act_handler
},
[RTE_FLOW_ACTION_TYPE_PHY_PORT] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_phy_port_act_handler
},
[RTE_FLOW_ACTION_TYPE_PORT_ID] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_port_id_act_handler
},
[RTE_FLOW_ACTION_TYPE_METER] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SECURITY] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_of_pop_vlan_act_handler
},
[RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_of_push_vlan_act_handler
},
[RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_of_set_vlan_vid_act_handler
},
[RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_of_set_vlan_pcp_act_handler
},
[RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_vxlan_encap_act_handler
},
[RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_vxlan_decap_act_handler
},
[RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_RAW_DECAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_set_ipv4_src_act_handler
},
[RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_set_ipv4_dst_act_handler
},
[RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_set_tp_src_act_handler
},
[RTE_FLOW_ACTION_TYPE_SET_TP_DST] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_set_tp_dst_act_handler
},
[RTE_FLOW_ACTION_TYPE_MAC_SWAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_DEC_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_dec_ttl_act_handler
},
[RTE_FLOW_ACTION_TYPE_SET_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
}
};
/*
* This table has to be indexed based on the rte_flow_item_type that is part of
* DPDK. The below array is list of parsing functions for each of the flow items
* that are supported.
*/
struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
[RTE_FLOW_ITEM_TYPE_END] = {
.hdr_type = BNXT_ULP_HDR_TYPE_END,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_VOID] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_void_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_INVERT] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ANY] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_PF] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_pf_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_VF] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_vf_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_PHY_PORT] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_phy_port_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_PORT_ID] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_port_id_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_RAW] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ETH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_eth_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_VLAN] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_vlan_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_IPV4] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_ipv4_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_IPV6] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_ipv6_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_ICMP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_UDP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_udp_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_TCP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_tcp_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_SCTP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_VXLAN] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_vxlan_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_E_TAG] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_NVGRE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_MPLS] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GRE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_FUZZY] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GTP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GTPC] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GTPU] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ESP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GENEVE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_IPV6_EXT] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_MARK] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_META] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GRE_KEY] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GTP_PSC] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_PPPOES] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_PPPOED] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_NSH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_IGMP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_AH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_HIGIG2] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
}
};

47
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
View File

@ -3,7 +3,6 @@
* All rights reserved.
*/
#include <rte_vxlan.h>
#include "bnxt.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
@ -228,11 +227,6 @@ bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params)
BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
parif);
/* populate the loopback parif */
ULP_COMP_FLD_IDX_WR(params,
BNXT_ULP_CF_IDX_LOOPBACK_PARIF,
BNXT_ULP_SYM_VF_FUNC_PARIF);
} else {
/* Set DRV func PARIF */
if (ulp_port_db_parif_get(params->ulp_ctx, ifindex,
@ -301,6 +295,9 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
/* Merge the hdr_fp_bit into the proto header bit */
params->hdr_bitmap.bits |= params->hdr_fp_bit.bits;
/* Update the comp fld fid */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FID, params->fid);
/* Update the computed interface parameters */
bnxt_ulp_comp_fld_intf_update(params);
@ -686,10 +683,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_mask_copy(params, &idx, &eth_mask->type,
sizeof(eth_mask->type));
}
/* Add number of vlan header elements */
/* Add number of Eth header elements */
params->field_idx += BNXT_ULP_PROTO_HDR_ETH_NUM;
params->vlan_idx = params->field_idx;
params->field_idx += BNXT_ULP_PROTO_HDR_VLAN_NUM;
/* Update the protocol hdr bitmap */
if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
@ -722,7 +717,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_vlan *vlan_mask = item->mask;
struct ulp_rte_hdr_field *field;
struct ulp_rte_hdr_bitmap *hdr_bit;
uint32_t idx = params->vlan_idx;
uint32_t idx = params->field_idx;
uint16_t vlan_tag, priority;
uint32_t outer_vtag_num;
uint32_t inner_vtag_num;
@ -781,8 +776,8 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_mask_copy(params, &idx, &vlan_mask->inner_type,
sizeof(vlan_mask->inner_type));
}
/* Set the vlan index to new incremented value */
params->vlan_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM;
/* Set the field index to new incremented value */
params->field_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM;
/* Get the outer tag and inner tag counts */
outer_vtag_num = ULP_COMP_FLD_IDX_RD(params,
@ -1013,13 +1008,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
}
/* Some of the PMD applications may set the protocol field
* in the IPv4 spec but don't set the mask. So, consider
* the mask in the proto value calculation.
*/
if (ipv4_mask)
proto &= ipv4_mask->hdr.next_proto_id;
/* Update the field protocol hdr bitmap */
ulp_rte_l3_proto_type_update(params, proto, inner_flag);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt);
@ -1117,8 +1105,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
&vtcf_mask,
size);
/*
* The TC and flow label field are ignored since OVS is
* setting it for match and it is not supported.
* The TC and flow label field are ignored since OVS is setting
* it for match and it is not supported.
* This is a work around and
* shall be addressed in the future.
*/
@ -1158,13 +1146,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
}
/* Some of the PMD applications may set the protocol field
* in the IPv6 spec but don't set the mask. So, consider
* the mask in proto value calculation.
*/
if (ipv6_mask)
proto &= ipv6_mask->hdr.proto;
/* Update the field protocol hdr bitmap */
ulp_rte_l3_proto_type_update(params, proto, inner_flag);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt);
@ -1549,7 +1530,7 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
buff = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG];
ulp_encap_buffer_copy(buff,
item->spec,
sizeof(struct rte_vlan_hdr),
sizeof(struct rte_flow_item_vlan),
ULP_BUFFER_ALIGN_8_BYTE);
if (!ulp_rte_item_skip_void(&item, 1))
@ -1560,15 +1541,15 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
vlan_num++;
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG +
sizeof(struct rte_vlan_hdr)],
sizeof(struct rte_flow_item_vlan)],
item->spec,
sizeof(struct rte_vlan_hdr));
sizeof(struct rte_flow_item_vlan));
if (!ulp_rte_item_skip_void(&item, 1))
return BNXT_TF_RC_ERROR;
}
/* Update the vlan count and size of more than one */
if (vlan_num) {
vlan_size = vlan_num * sizeof(struct rte_vlan_hdr);
vlan_size = vlan_num * sizeof(struct rte_flow_item_vlan);
vlan_num = tfp_cpu_to_be_32(vlan_num);
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM],
&vlan_num,
@ -1727,7 +1708,7 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
BNXT_TF_DBG(ERR, "vxlan encap does not have vni\n");
return BNXT_TF_RC_ERROR;
}
vxlan_size = sizeof(struct rte_vxlan_hdr);
vxlan_size = sizeof(struct rte_flow_item_vxlan);
/* copy the vxlan details */
memcpy(&vxlan_spec, item->spec, vxlan_size);
vxlan_spec.flags = 0x08;

768
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
View File

@ -3,813 +3,141 @@
* All rights reserved.
*/
/* date: Mon Nov 23 17:33:02 2020 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
#include "ulp_rte_parser.h"
#include "ulp_template_db_tbl.h"
/*
* Action signature table:
* maps hash id to ulp_act_match_list[] index
*/
uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_ACT_HID_015a] = 1,
[BNXT_ULP_ACT_HID_00eb] = 2,
[BNXT_ULP_ACT_HID_0043] = 3,
[BNXT_ULP_ACT_HID_03d8] = 4,
[BNXT_ULP_ACT_HID_02c1] = 5,
[BNXT_ULP_ACT_HID_015e] = 6,
[BNXT_ULP_ACT_HID_00ef] = 7,
[BNXT_ULP_ACT_HID_0047] = 8,
[BNXT_ULP_ACT_HID_03dc] = 9,
[BNXT_ULP_ACT_HID_02c5] = 10,
[BNXT_ULP_ACT_HID_025b] = 11,
[BNXT_ULP_ACT_HID_01ec] = 12,
[BNXT_ULP_ACT_HID_0144] = 13,
[BNXT_ULP_ACT_HID_04d9] = 14,
[BNXT_ULP_ACT_HID_03c2] = 15,
[BNXT_ULP_ACT_HID_025f] = 16,
[BNXT_ULP_ACT_HID_01f0] = 17,
[BNXT_ULP_ACT_HID_0148] = 18,
[BNXT_ULP_ACT_HID_04dd] = 19,
[BNXT_ULP_ACT_HID_03c6] = 20,
[BNXT_ULP_ACT_HID_0000] = 21,
[BNXT_ULP_ACT_HID_0002] = 22,
[BNXT_ULP_ACT_HID_0800] = 23,
[BNXT_ULP_ACT_HID_0101] = 24,
[BNXT_ULP_ACT_HID_0020] = 25,
[BNXT_ULP_ACT_HID_0901] = 26,
[BNXT_ULP_ACT_HID_0121] = 27,
[BNXT_ULP_ACT_HID_0004] = 28,
[BNXT_ULP_ACT_HID_0006] = 29,
[BNXT_ULP_ACT_HID_0804] = 30,
[BNXT_ULP_ACT_HID_0105] = 31,
[BNXT_ULP_ACT_HID_0024] = 32,
[BNXT_ULP_ACT_HID_0905] = 33,
[BNXT_ULP_ACT_HID_0125] = 34,
[BNXT_ULP_ACT_HID_0001] = 35,
[BNXT_ULP_ACT_HID_0005] = 36,
[BNXT_ULP_ACT_HID_0009] = 37,
[BNXT_ULP_ACT_HID_000d] = 38,
[BNXT_ULP_ACT_HID_0021] = 39,
[BNXT_ULP_ACT_HID_0029] = 40,
[BNXT_ULP_ACT_HID_0025] = 41,
[BNXT_ULP_ACT_HID_002d] = 42,
[BNXT_ULP_ACT_HID_0801] = 43,
[BNXT_ULP_ACT_HID_0809] = 44,
[BNXT_ULP_ACT_HID_0805] = 45,
[BNXT_ULP_ACT_HID_080d] = 46,
[BNXT_ULP_ACT_HID_0c15] = 47,
[BNXT_ULP_ACT_HID_0c19] = 48,
[BNXT_ULP_ACT_HID_02f6] = 49,
[BNXT_ULP_ACT_HID_04f8] = 50,
[BNXT_ULP_ACT_HID_01df] = 51,
[BNXT_ULP_ACT_HID_07e5] = 52,
[BNXT_ULP_ACT_HID_06ce] = 53,
[BNXT_ULP_ACT_HID_02fa] = 54,
[BNXT_ULP_ACT_HID_04fc] = 55,
[BNXT_ULP_ACT_HID_01e3] = 56,
[BNXT_ULP_ACT_HID_07e9] = 57,
[BNXT_ULP_ACT_HID_06d2] = 58,
[BNXT_ULP_ACT_HID_03f7] = 59,
[BNXT_ULP_ACT_HID_05f9] = 60,
[BNXT_ULP_ACT_HID_02e0] = 61,
[BNXT_ULP_ACT_HID_08e6] = 62,
[BNXT_ULP_ACT_HID_07cf] = 63,
[BNXT_ULP_ACT_HID_03fb] = 64,
[BNXT_ULP_ACT_HID_05fd] = 65,
[BNXT_ULP_ACT_HID_02e4] = 66,
[BNXT_ULP_ACT_HID_08ea] = 67,
[BNXT_ULP_ACT_HID_07d3] = 68,
[BNXT_ULP_ACT_HID_040d] = 69,
[BNXT_ULP_ACT_HID_040f] = 70,
[BNXT_ULP_ACT_HID_0413] = 71,
[BNXT_ULP_ACT_HID_0567] = 72,
[BNXT_ULP_ACT_HID_0a49] = 73,
[BNXT_ULP_ACT_HID_050e] = 74,
[BNXT_ULP_ACT_HID_0668] = 75,
[BNXT_ULP_ACT_HID_0b4a] = 76,
[BNXT_ULP_ACT_HID_0411] = 77,
[BNXT_ULP_ACT_HID_056b] = 78,
[BNXT_ULP_ACT_HID_0a4d] = 79,
[BNXT_ULP_ACT_HID_0512] = 80,
[BNXT_ULP_ACT_HID_066c] = 81,
[BNXT_ULP_ACT_HID_0b4e] = 82
[BNXT_ULP_ACT_HID_0000] = 1,
[BNXT_ULP_ACT_HID_0001] = 2,
[BNXT_ULP_ACT_HID_0400] = 3,
[BNXT_ULP_ACT_HID_0331] = 4,
[BNXT_ULP_ACT_HID_0010] = 5,
[BNXT_ULP_ACT_HID_0731] = 6,
[BNXT_ULP_ACT_HID_0341] = 7,
[BNXT_ULP_ACT_HID_0002] = 8,
[BNXT_ULP_ACT_HID_0003] = 9,
[BNXT_ULP_ACT_HID_0402] = 10,
[BNXT_ULP_ACT_HID_0333] = 11,
[BNXT_ULP_ACT_HID_0012] = 12,
[BNXT_ULP_ACT_HID_0733] = 13,
[BNXT_ULP_ACT_HID_0343] = 14
};
/* Array for the act matcher list */
struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
[1] = {
.act_hid = BNXT_ULP_ACT_HID_015a,
.act_hid = BNXT_ULP_ACT_HID_0000,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[2] = {
.act_hid = BNXT_ULP_ACT_HID_00eb,
.act_hid = BNXT_ULP_ACT_HID_0001,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[3] = {
.act_hid = BNXT_ULP_ACT_HID_0043,
.act_hid = BNXT_ULP_ACT_HID_0400,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[4] = {
.act_hid = BNXT_ULP_ACT_HID_03d8,
.act_hid = BNXT_ULP_ACT_HID_0331,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[5] = {
.act_hid = BNXT_ULP_ACT_HID_02c1,
.act_hid = BNXT_ULP_ACT_HID_0010,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[6] = {
.act_hid = BNXT_ULP_ACT_HID_015e,
.act_hid = BNXT_ULP_ACT_HID_0731,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[7] = {
.act_hid = BNXT_ULP_ACT_HID_00ef,
.act_hid = BNXT_ULP_ACT_HID_0341,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[8] = {
.act_hid = BNXT_ULP_ACT_HID_0047,
.act_hid = BNXT_ULP_ACT_HID_0002,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[9] = {
.act_hid = BNXT_ULP_ACT_HID_03dc,
.act_hid = BNXT_ULP_ACT_HID_0003,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_ACTION_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[10] = {
.act_hid = BNXT_ULP_ACT_HID_02c5,
.act_hid = BNXT_ULP_ACT_HID_0402,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[11] = {
.act_hid = BNXT_ULP_ACT_HID_025b,
.act_hid = BNXT_ULP_ACT_HID_0333,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[12] = {
.act_hid = BNXT_ULP_ACT_HID_01ec,
.act_hid = BNXT_ULP_ACT_HID_0012,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[13] = {
.act_hid = BNXT_ULP_ACT_HID_0144,
.act_hid = BNXT_ULP_ACT_HID_0733,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[14] = {
.act_hid = BNXT_ULP_ACT_HID_04d9,
.act_hid = BNXT_ULP_ACT_HID_0343,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[15] = {
.act_hid = BNXT_ULP_ACT_HID_03c2,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[16] = {
.act_hid = BNXT_ULP_ACT_HID_025f,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[17] = {
.act_hid = BNXT_ULP_ACT_HID_01f0,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[18] = {
.act_hid = BNXT_ULP_ACT_HID_0148,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[19] = {
.act_hid = BNXT_ULP_ACT_HID_04dd,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[20] = {
.act_hid = BNXT_ULP_ACT_HID_03c6,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[21] = {
.act_hid = BNXT_ULP_ACT_HID_0000,
.act_sig = { .bits =
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[22] = {
.act_hid = BNXT_ULP_ACT_HID_0002,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[23] = {
.act_hid = BNXT_ULP_ACT_HID_0800,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[24] = {
.act_hid = BNXT_ULP_ACT_HID_0101,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[25] = {
.act_hid = BNXT_ULP_ACT_HID_0020,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[26] = {
.act_hid = BNXT_ULP_ACT_HID_0901,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[27] = {
.act_hid = BNXT_ULP_ACT_HID_0121,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[28] = {
.act_hid = BNXT_ULP_ACT_HID_0004,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[29] = {
.act_hid = BNXT_ULP_ACT_HID_0006,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[30] = {
.act_hid = BNXT_ULP_ACT_HID_0804,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[31] = {
.act_hid = BNXT_ULP_ACT_HID_0105,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[32] = {
.act_hid = BNXT_ULP_ACT_HID_0024,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[33] = {
.act_hid = BNXT_ULP_ACT_HID_0905,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[34] = {
.act_hid = BNXT_ULP_ACT_HID_0125,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
},
[35] = {
.act_hid = BNXT_ULP_ACT_HID_0001,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[36] = {
.act_hid = BNXT_ULP_ACT_HID_0005,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[37] = {
.act_hid = BNXT_ULP_ACT_HID_0009,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[38] = {
.act_hid = BNXT_ULP_ACT_HID_000d,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[39] = {
.act_hid = BNXT_ULP_ACT_HID_0021,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[40] = {
.act_hid = BNXT_ULP_ACT_HID_0029,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[41] = {
.act_hid = BNXT_ULP_ACT_HID_0025,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[42] = {
.act_hid = BNXT_ULP_ACT_HID_002d,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[43] = {
.act_hid = BNXT_ULP_ACT_HID_0801,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[44] = {
.act_hid = BNXT_ULP_ACT_HID_0809,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[45] = {
.act_hid = BNXT_ULP_ACT_HID_0805,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[46] = {
.act_hid = BNXT_ULP_ACT_HID_080d,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[47] = {
.act_hid = BNXT_ULP_ACT_HID_0c15,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[48] = {
.act_hid = BNXT_ULP_ACT_HID_0c19,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[49] = {
.act_hid = BNXT_ULP_ACT_HID_02f6,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[50] = {
.act_hid = BNXT_ULP_ACT_HID_04f8,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[51] = {
.act_hid = BNXT_ULP_ACT_HID_01df,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[52] = {
.act_hid = BNXT_ULP_ACT_HID_07e5,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[53] = {
.act_hid = BNXT_ULP_ACT_HID_06ce,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[54] = {
.act_hid = BNXT_ULP_ACT_HID_02fa,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[55] = {
.act_hid = BNXT_ULP_ACT_HID_04fc,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[56] = {
.act_hid = BNXT_ULP_ACT_HID_01e3,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[57] = {
.act_hid = BNXT_ULP_ACT_HID_07e9,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[58] = {
.act_hid = BNXT_ULP_ACT_HID_06d2,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[59] = {
.act_hid = BNXT_ULP_ACT_HID_03f7,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[60] = {
.act_hid = BNXT_ULP_ACT_HID_05f9,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[61] = {
.act_hid = BNXT_ULP_ACT_HID_02e0,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[62] = {
.act_hid = BNXT_ULP_ACT_HID_08e6,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[63] = {
.act_hid = BNXT_ULP_ACT_HID_07cf,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[64] = {
.act_hid = BNXT_ULP_ACT_HID_03fb,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[65] = {
.act_hid = BNXT_ULP_ACT_HID_05fd,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[66] = {
.act_hid = BNXT_ULP_ACT_HID_02e4,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[67] = {
.act_hid = BNXT_ULP_ACT_HID_08ea,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[68] = {
.act_hid = BNXT_ULP_ACT_HID_07d3,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC |
BNXT_ULP_ACTION_BIT_SET_IPV4_DST |
BNXT_ULP_ACTION_BIT_SET_TP_SRC |
BNXT_ULP_ACTION_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[69] = {
.act_hid = BNXT_ULP_ACT_HID_040d,
.act_sig = { .bits =
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[70] = {
.act_hid = BNXT_ULP_ACT_HID_040f,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[71] = {
.act_hid = BNXT_ULP_ACT_HID_0413,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DROP |
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[72] = {
.act_hid = BNXT_ULP_ACT_HID_0567,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_VLAN_PCP |
BNXT_ULP_ACTION_BIT_SET_VLAN_VID |
BNXT_ULP_ACTION_BIT_PUSH_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[73] = {
.act_hid = BNXT_ULP_ACT_HID_0a49,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_SET_VLAN_VID |
BNXT_ULP_ACTION_BIT_PUSH_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[74] = {
.act_hid = BNXT_ULP_ACT_HID_050e,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[75] = {
.act_hid = BNXT_ULP_ACT_HID_0668,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_VLAN_PCP |
BNXT_ULP_ACTION_BIT_SET_VLAN_VID |
BNXT_ULP_ACTION_BIT_PUSH_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[76] = {
.act_hid = BNXT_ULP_ACT_HID_0b4a,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_VLAN_VID |
BNXT_ULP_ACTION_BIT_PUSH_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[77] = {
.act_hid = BNXT_ULP_ACT_HID_0411,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[78] = {
.act_hid = BNXT_ULP_ACT_HID_056b,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_VLAN_PCP |
BNXT_ULP_ACTION_BIT_SET_VLAN_VID |
BNXT_ULP_ACTION_BIT_PUSH_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[79] = {
.act_hid = BNXT_ULP_ACT_HID_0a4d,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_SET_VLAN_VID |
BNXT_ULP_ACTION_BIT_PUSH_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[80] = {
.act_hid = BNXT_ULP_ACT_HID_0512,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[81] = {
.act_hid = BNXT_ULP_ACT_HID_066c,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_VLAN_PCP |
BNXT_ULP_ACTION_BIT_SET_VLAN_VID |
BNXT_ULP_ACTION_BIT_PUSH_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[82] = {
.act_hid = BNXT_ULP_ACT_HID_0b4e,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_ACTION_BIT_DEC_TTL |
BNXT_ULP_ACTION_BIT_SET_VLAN_VID |
BNXT_ULP_ACTION_BIT_PUSH_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
}
};

4144
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
View File

File diff suppressed because it is too large Load Diff

1233
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
View File

File diff suppressed because it is too large Load Diff

1378
drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
View File

File diff suppressed because it is too large Load Diff

4320
drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
View File

File diff suppressed because it is too large Load Diff

28347
drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
View File

File diff suppressed because it is too large Load Diff

1106
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
View File

File diff suppressed because it is too large Load Diff

24
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h
View File

@ -16,10 +16,10 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[];
extern struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[];
extern struct
bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[];
bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[];
extern struct
bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[];
bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[];
extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[];
@ -28,7 +28,13 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[];
extern struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[];
extern struct
bnxt_ulp_mapper_result_field_info ulp_wh_plus_act_result_field_list[];
bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[];
extern struct
bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[];
extern struct
bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[];
/* STINGRAY template table declarations */
extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[];
@ -36,10 +42,10 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[];
extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[];
extern struct
bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[];
bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[];
extern struct
bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[];
bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[];
extern struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[];
@ -48,7 +54,13 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[];
extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[];
extern struct
bnxt_ulp_mapper_result_field_info ulp_stingray_act_result_field_list[];
bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[];
extern struct
bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[];
extern struct
bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[];
extern uint8_t ulp_glb_field_tbl[];
#endif

4317
drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
View File

File diff suppressed because it is too large Load Diff

28628
drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
View File

File diff suppressed because it is too large Load Diff

61
drivers/net/bnxt/tf_ulp/ulp_template_struct.h
View File

@ -18,7 +18,7 @@
#include "tf_core.h"
/* Number of fields for each protocol */
#define BNXT_ULP_PROTO_HDR_SVIF_NUM 1
#define BNXT_ULP_PROTO_HDR_SVIF_NUM 2
#define BNXT_ULP_PROTO_HDR_ETH_NUM 3
#define BNXT_ULP_PROTO_HDR_S_VLAN_NUM 3
#define BNXT_ULP_PROTO_HDR_VLAN_NUM 6
@ -28,7 +28,7 @@
#define BNXT_ULP_PROTO_HDR_TCP_NUM 9
#define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4
#define BNXT_ULP_PROTO_HDR_MAX 128
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 0
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1
/* Direction attributes */
#define BNXT_ULP_FLOW_ATTR_TRANSFER 0x1
@ -62,14 +62,12 @@ struct ulp_rte_act_prop {
/* Structure to be used for passing all the parser functions */
struct ulp_rte_parser_params {
STAILQ_ENTRY(ulp_rte_parser_params) next;
struct ulp_rte_hdr_bitmap hdr_bitmap;
struct ulp_rte_hdr_bitmap hdr_fp_bit;
struct ulp_rte_field_bitmap fld_bitmap;
struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX];
uint32_t comp_fld[BNXT_ULP_CF_IDX_LAST];
uint32_t field_idx;
uint32_t vlan_idx;
struct ulp_rte_act_bitmap act_bitmap;
struct ulp_rte_act_prop act_prop;
uint32_t dir_attr;
@ -78,10 +76,11 @@ struct ulp_rte_parser_params {
uint32_t parent_flow;
uint32_t parent_fid;
uint16_t func_id;
uint16_t port_id;
uint32_t class_id;
uint32_t act_tmpl;
struct bnxt_ulp_context *ulp_ctx;
uint32_t hdr_sig_id;
uint32_t flow_sig_id;
};
/* Flow Parser Header Information Structure */
@ -127,6 +126,8 @@ struct bnxt_ulp_class_match_info {
uint32_t class_tid;
uint8_t act_vnic;
uint8_t wc_pri;
uint32_t hdr_sig_id;
uint32_t flow_sig_id;
};
/* Flow Matcher templates Structure for class entries */
@ -163,11 +164,17 @@ struct bnxt_ulp_mapper_cond_list_info {
struct bnxt_ulp_template_device_tbls {
struct bnxt_ulp_mapper_tmpl_info *tmpl_list;
uint32_t tmpl_list_size;
struct bnxt_ulp_mapper_tbl_info *tbl_list;
struct bnxt_ulp_mapper_key_field_info *key_field_list;
struct bnxt_ulp_mapper_result_field_info *result_field_list;
uint32_t tbl_list_size;
struct bnxt_ulp_mapper_key_info *key_info_list;
uint32_t key_info_list_size;
struct bnxt_ulp_mapper_field_info *result_field_list;
uint32_t result_field_list_size;
struct bnxt_ulp_mapper_ident_info *ident_list;
uint32_t ident_list_size;
struct bnxt_ulp_mapper_cond_info *cond_list;
uint32_t cond_list_size;
};
/* Device specific parameters */
@ -210,6 +217,10 @@ struct bnxt_ulp_mapper_tbl_info {
uint8_t direction;
enum bnxt_ulp_pri_opc pri_opcode;
uint32_t pri_operand;
/* conflict resolution opcode */
enum bnxt_ulp_accept_opc accept_opcode;
enum bnxt_ulp_critical_resource critical_resource;
/* Information for accessing the ulp_key_field_list */
@ -237,25 +248,21 @@ struct bnxt_ulp_mapper_tbl_info {
/* FDB table opcode */
enum bnxt_ulp_fdb_opc fdb_opcode;
uint32_t flow_db_operand;
uint32_t fdb_operand;
};
struct bnxt_ulp_mapper_key_field_info {
uint8_t description[64];
enum bnxt_ulp_mapper_opc mask_opcode;
enum bnxt_ulp_mapper_opc spec_opcode;
uint16_t field_bit_size;
uint8_t mask_operand[16];
uint8_t spec_operand[16];
struct bnxt_ulp_mapper_field_info {
uint8_t description[64];
enum bnxt_ulp_field_opc field_opcode;
uint16_t field_bit_size;
uint8_t field_operand[16];
uint8_t field_operand_true[16];
uint8_t field_operand_false[16];
};
struct bnxt_ulp_mapper_result_field_info {
uint8_t description[64];
enum bnxt_ulp_mapper_opc result_opcode;
uint16_t field_bit_size;
uint8_t result_operand[16];
uint8_t result_operand_true[16];
uint8_t result_operand_false[16];
struct bnxt_ulp_mapper_key_info {
struct bnxt_ulp_mapper_field_info field_info_spec;
struct bnxt_ulp_mapper_field_info field_info_mask;
};
struct bnxt_ulp_mapper_ident_info {
@ -265,13 +272,13 @@ struct bnxt_ulp_mapper_ident_info {
uint16_t ident_type;
uint16_t ident_bit_size;
uint16_t ident_bit_pos;
enum bnxt_ulp_regfile_index regfile_idx;
enum bnxt_ulp_rf_idx regfile_idx;
};
struct bnxt_ulp_glb_resource_info {
enum bnxt_ulp_resource_func resource_func;
uint32_t resource_type; /* TF_ enum type */
enum bnxt_ulp_glb_regfile_index glb_regfile_index;
enum bnxt_ulp_glb_rf_idx glb_regfile_index;
enum tf_dir direction;
};
@ -281,10 +288,14 @@ struct bnxt_ulp_cache_tbl_params {
struct bnxt_ulp_generic_tbl_params {
uint16_t result_num_entries;
uint16_t result_byte_size;
uint16_t result_num_bytes;
enum bnxt_ulp_byte_order result_byte_order;
};
struct bnxt_ulp_shared_act_info {
uint64_t act_bitmask;
};
/*
* Flow Mapper Static Data Externs:
* Access to the below static data should be done through access functions and

221
drivers/net/bnxt/tf_ulp/ulp_tun.c
View File

@ -3,8 +3,6 @@
* All rights reserved.
*/
#include <sys/queue.h>
#include <rte_malloc.h>
#include "ulp_tun.h"
@ -50,18 +48,18 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
goto err;
/* Store the tunnel dmac in the tunnel cache table and use it while
* programming tunnel inner flow.
* programming tunnel flow F2.
*/
memcpy(tun_entry->t_dmac,
&params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec,
RTE_ETHER_ADDR_LEN);
tun_entry->tun_flow_info[params->port_id].state =
BNXT_ULP_FLOW_STATE_TUN_O_OFFLD;
tun_entry->valid = true;
tun_entry->state = BNXT_ULP_FLOW_STATE_TUN_O_OFFLD;
tun_entry->outer_tun_flow_id = params->fid;
/* Tunnel outer flow and it's related inner flows are correlated
* based on Tunnel Destination IP Address.
/* F1 and it's related F2s are correlated based on
* Tunnel Destination IP Address.
*/
if (tun_entry->t_dst_ip_valid)
goto done;
@ -85,32 +83,27 @@ err:
/* This function programs the inner tunnel flow in the hardware. */
static void
ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry,
struct ulp_rte_parser_params *tun_o_params)
ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry)
{
struct bnxt_ulp_mapper_create_parms mparms = { 0 };
struct ulp_per_port_flow_info *flow_info;
struct ulp_rte_parser_params *inner_params;
struct ulp_rte_parser_params *params;
int ret;
/* Tunnel inner flow doesn't have tunnel dmac, use the tunnel
* dmac that was stored during F1 programming.
/* F2 doesn't have tunnel dmac, use the tunnel dmac that was
* stored during F1 programming.
*/
flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id];
STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) {
memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
inner_params->parent_fid = tun_entry->outer_tun_flow_id;
params = &tun_entry->first_inner_tun_params;
memcpy(&params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
params->parent_fid = tun_entry->outer_tun_flow_id;
params->fid = tun_entry->first_inner_tun_flow_id;
bnxt_ulp_init_mapper_params(&mparms, inner_params,
BNXT_ULP_FDB_TYPE_REGULAR);
bnxt_ulp_init_mapper_params(&mparms, params,
BNXT_ULP_FDB_TYPE_REGULAR);
ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms);
if (ret)
PMD_DRV_LOG(ERR,
"Failed to create inner tun flow, FID:%u.",
inner_params->fid);
}
ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);
if (ret)
PMD_DRV_LOG(ERR, "Failed to create F2 flow.");
}
/* This function either install outer tunnel flow & inner tunnel flow
@ -121,31 +114,30 @@ ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry *tun_entry,
uint16_t tun_idx)
{
enum bnxt_ulp_tun_flow_state flow_state;
int ret;
flow_state = tun_entry->state;
ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx);
if (ret == BNXT_TF_RC_ERROR) {
PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow.");
if (ret)
return ret;
}
/* Install any cached tunnel inner flows that came before tunnel
* outer flow.
/* If flow_state == BNXT_ULP_FLOW_STATE_NORMAL before installing
* F1, that means F2 is not deferred. Hence, no need to install F2.
*/
ulp_install_inner_tun_flow(tun_entry, params);
if (flow_state != BNXT_ULP_FLOW_STATE_NORMAL)
ulp_install_inner_tun_flow(tun_entry);
return BNXT_TF_RC_FID;
return 0;
}
/* This function will be called if inner tunnel flow request comes before
* outer tunnel flow request.
*/
static int32_t
ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
ulp_post_process_first_inner_tun_flow(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry *tun_entry)
{
struct ulp_rte_parser_params *inner_tun_params;
struct ulp_per_port_flow_info *flow_info;
int ret;
ret = ulp_matcher_pattern_match(params, &params->class_id);
@ -156,22 +148,18 @@ ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
if (ret != BNXT_TF_RC_SUCCESS)
return BNXT_TF_RC_ERROR;
/* If Tunnel inner flow comes first then we can't install it in the
* hardware, because, Tunnel inner flow will not have L2 context
* information. So, just cache the Tunnel inner flow information
* and program it in the context of F1 flow installation.
/* If Tunnel F2 flow comes first then we can't install it in the
* hardware, because, F2 flow will not have L2 context information.
* So, just cache the F2 information and program it in the context
* of F1 flow installation.
*/
flow_info = &tun_entry->tun_flow_info[params->port_id];
inner_tun_params = rte_zmalloc("ulp_inner_tun_params",
sizeof(struct ulp_rte_parser_params), 0);
if (!inner_tun_params)
return BNXT_TF_RC_ERROR;
memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params));
STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params,
next);
flow_info->tun_i_cnt++;
memcpy(&tun_entry->first_inner_tun_params, params,
sizeof(struct ulp_rte_parser_params));
/* F1 and it's related Tunnel inner flows are correlated based on
tun_entry->first_inner_tun_flow_id = params->fid;
tun_entry->state = BNXT_ULP_FLOW_STATE_TUN_I_CACHED;
/* F1 and it's related F2s are correlated based on
* Tunnel Destination IP Address. It could be already set, if
* the inner flow got offloaded first.
*/
@ -252,8 +240,8 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params,
int32_t
ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
{
bool inner_tun_sig, cache_inner_tun_flow;
bool outer_tun_reject, outer_tun_flow, inner_tun_flow;
bool outer_tun_sig, inner_tun_sig, first_inner_tun_flow;
bool outer_tun_reject, inner_tun_reject, outer_tun_flow, inner_tun_flow;
enum bnxt_ulp_tun_flow_state flow_state;
struct bnxt_tun_cache_entry *tun_entry;
uint32_t l3_tun, l3_tun_decap;
@ -271,31 +259,40 @@ ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
if (rc == BNXT_TF_RC_ERROR)
return rc;
if (params->port_id >= RTE_MAX_ETHPORTS)
return BNXT_TF_RC_ERROR;
flow_state = tun_entry->tun_flow_info[params->port_id].state;
flow_state = tun_entry->state;
/* Outer tunnel flow validation */
outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params);
outer_tun_sig = BNXT_OUTER_TUN_SIGNATURE(l3_tun, params);
outer_tun_flow = BNXT_OUTER_TUN_FLOW(outer_tun_sig);
outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state,
outer_tun_flow);
outer_tun_sig);
/* Inner tunnel flow validation */
inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params);
cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state,
first_inner_tun_flow = BNXT_FIRST_INNER_TUN_FLOW(flow_state,
inner_tun_sig);
inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig);
inner_tun_reject = BNXT_REJECT_INNER_TUN_FLOW(flow_state,
inner_tun_sig);
if (outer_tun_reject) {
tun_entry->outer_tun_rej_cnt++;
BNXT_TF_DBG(ERR,
"Tunnel F1 flow rejected, COUNT: %d\n",
tun_entry->outer_tun_rej_cnt);
/* Inner tunnel flow is rejected if it comes between first inner
* tunnel flow and outer flow requests.
*/
} else if (inner_tun_reject) {
tun_entry->inner_tun_rej_cnt++;
BNXT_TF_DBG(ERR,
"Tunnel F2 flow rejected, COUNT: %d\n",
tun_entry->inner_tun_rej_cnt);
}
if (outer_tun_reject)
if (outer_tun_reject || inner_tun_reject)
return BNXT_TF_RC_ERROR;
else if (cache_inner_tun_flow)
return ulp_post_process_cache_inner_tun_flow(params, tun_entry);
else if (first_inner_tun_flow)
return ulp_post_process_first_inner_tun_flow(params, tun_entry);
else if (outer_tun_flow)
return ulp_post_process_outer_tun_flow(params, tun_entry,
tun_idx);
@ -305,109 +302,9 @@ ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
return BNXT_TF_RC_NORMAL;
}
void
ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl)
{
struct ulp_per_port_flow_info *flow_info;
int i, j;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
flow_info = &tun_tbl[i].tun_flow_info[j];
STAILQ_INIT(&flow_info->tun_i_prms_list);
}
}
}
void
ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx)
{
struct ulp_rte_parser_params *inner_params;
struct ulp_per_port_flow_info *flow_info;
int j;
for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
STAILQ_FOREACH(inner_params,
&flow_info->tun_i_prms_list,
next) {
STAILQ_REMOVE(&flow_info->tun_i_prms_list,
inner_params,
ulp_rte_parser_params, next);
rte_free(inner_params);
}
}
memset(&tun_tbl[tun_idx], 0,
sizeof(struct bnxt_tun_cache_entry));
for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
STAILQ_INIT(&flow_info->tun_i_prms_list);
}
}
static bool
ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry,
struct ulp_per_port_flow_info *flow_info,
uint32_t fid)
{
struct ulp_rte_parser_params *inner_params;
int j;
STAILQ_FOREACH(inner_params,
&flow_info->tun_i_prms_list,
next) {
if (inner_params->fid == fid) {
STAILQ_REMOVE(&flow_info->tun_i_prms_list,
inner_params,
ulp_rte_parser_params,
next);
rte_free(inner_params);
flow_info->tun_i_cnt--;
/* When a dpdk application offloads a duplicate
* tunnel inner flow on a port that it is not
* destined to, there won't be a tunnel outer flow
* associated with these duplicate tunnel inner flows.
* So, when the last tunnel inner flow ages out, the
* driver has to clear the tunnel entry, otherwise
* the tunnel entry cannot be reused.
*/
if (!flow_info->tun_i_cnt &&
flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) {
memset(tun_entry, 0,
sizeof(struct bnxt_tun_cache_entry));
for (j = 0; j < RTE_MAX_ETHPORTS; j++)
STAILQ_INIT(&flow_info->tun_i_prms_list);
}
return true;
}
}
return false;
}
/* When a dpdk application offloads the same tunnel inner flow
* on all the uplink ports, a tunnel inner flow entry is cached
* even if it is not for the right uplink port. Such tunnel
* inner flows will eventually get aged out as there won't be
* any traffic on these ports. When such a flow destroy is
* called, cleanup the tunnel inner flow entry.
*/
void
ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid)
{
struct ulp_per_port_flow_info *flow_info;
int i, j;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
if (!tun_tbl[i].t_dst_ip_valid)
continue;
for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
flow_info = &tun_tbl[i].tun_flow_info[j];
if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i],
flow_info, fid) == true)
return;
}
}
sizeof(struct bnxt_tun_cache_entry));
}

37
drivers/net/bnxt/tf_ulp/ulp_tun.h
View File

@ -15,7 +15,7 @@
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \
#define BNXT_OUTER_TUN_SIGNATURE(l3_tun, params) \
((l3_tun) && \
ULP_BITMAP_ISSET((params)->act_bitmap.bits, \
BNXT_ULP_ACTION_BIT_JUMP))
@ -24,16 +24,22 @@
!ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \
BNXT_ULP_HDR_BIT_O_ETH))
#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \
#define BNXT_FIRST_INNER_TUN_FLOW(state, inner_tun_sig) \
((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig))
#define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \
((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig))
#define BNXT_OUTER_TUN_FLOW(outer_tun_sig) ((outer_tun_sig))
/* It is invalid to get another outer flow offload request
* for the same tunnel, while the outer flow is already offloaded.
*/
#define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \
((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig))
/* It is invalid to get another inner flow offload request
* for the same tunnel, while the outer flow is not yet offloaded.
*/
#define BNXT_REJECT_INNER_TUN_FLOW(state, inner_tun_sig) \
((state) == BNXT_ULP_FLOW_STATE_TUN_I_CACHED && (inner_tun_sig))
#define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1
#define ULP_TUN_O_IPV4_DIP_INDEX 19
@ -44,10 +50,10 @@
* requests arrive.
*
* If inner tunnel flow offload request arrives first then the flow
* state will remain in BNXT_ULP_FLOW_STATE_NORMAL state.
* The following outer tunnel flow offload request will change the
* state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from
* BNXT_ULP_FLOW_STATE_NORMAL.
* state will change from BNXT_ULP_FLOW_STATE_NORMAL to
* BNXT_ULP_FLOW_STATE_TUN_I_CACHED and the following outer tunnel
* flow offload request will change the state of the flow to
* BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from BNXT_ULP_FLOW_STATE_TUN_I_CACHED.
*
* If outer tunnel flow offload request arrives first then the flow state
* will change from BNXT_ULP_FLOW_STATE_NORMAL to
@ -61,15 +67,12 @@
enum bnxt_ulp_tun_flow_state {
BNXT_ULP_FLOW_STATE_NORMAL = 0,
BNXT_ULP_FLOW_STATE_TUN_O_OFFLD,
};
struct ulp_per_port_flow_info {
enum bnxt_ulp_tun_flow_state state;
uint32_t tun_i_cnt;
STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list;
BNXT_ULP_FLOW_STATE_TUN_I_CACHED
};
struct bnxt_tun_cache_entry {
enum bnxt_ulp_tun_flow_state state;
bool valid;
bool t_dst_ip_valid;
uint8_t t_dmac[RTE_ETHER_ADDR_LEN];
union {
@ -77,17 +80,13 @@ struct bnxt_tun_cache_entry {
uint8_t t_dst_ip6[16];
};
uint32_t outer_tun_flow_id;
uint32_t first_inner_tun_flow_id;
uint16_t outer_tun_rej_cnt;
struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS];
uint16_t inner_tun_rej_cnt;
struct ulp_rte_parser_params first_inner_tun_params;
};
void
ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl);
void
ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx);
void
ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid);
#endif

16
drivers/net/bnxt/tf_ulp/ulp_utils.c
View File

@ -38,11 +38,11 @@ ulp_regfile_init(struct ulp_regfile *regfile)
*/
uint32_t
ulp_regfile_read(struct ulp_regfile *regfile,
enum bnxt_ulp_regfile_index field,
enum bnxt_ulp_rf_idx field,
uint64_t *data)
{
/* validate the arguments */
if (!regfile || field >= BNXT_ULP_REGFILE_INDEX_LAST) {
if (!regfile || field >= BNXT_ULP_RF_IDX_LAST) {
BNXT_TF_DBG(ERR, "invalid argument\n");
return 0; /* failure */
}
@ -64,21 +64,21 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* size [in] The size in bytes of the value beingritten into this
* variable.
*
* returns 0 on fail
* returns 0 on success
*/
uint32_t
int32_t
ulp_regfile_write(struct ulp_regfile *regfile,
enum bnxt_ulp_regfile_index field,
enum bnxt_ulp_rf_idx field,
uint64_t data)
{
/* validate the arguments */
if (!regfile || field >= BNXT_ULP_REGFILE_INDEX_LAST) {
if (!regfile || field >= BNXT_ULP_RF_IDX_LAST) {
BNXT_TF_DBG(ERR, "invalid argument\n");
return 0; /* failure */
return -EINVAL; /* failure */
}
regfile->entry[field].data = data;
return sizeof(data); /* Success */
return 0; /* Success */
}
static void

10
drivers/net/bnxt/tf_ulp/ulp_utils.h
View File

@ -91,7 +91,7 @@ struct ulp_regfile_entry {
};
struct ulp_regfile {
struct ulp_regfile_entry entry[BNXT_ULP_REGFILE_INDEX_LAST];
struct ulp_regfile_entry entry[BNXT_ULP_RF_IDX_LAST];
};
/*
@ -115,7 +115,7 @@ ulp_regfile_init(struct ulp_regfile *regfile);
*/
uint32_t
ulp_regfile_read(struct ulp_regfile *regfile,
enum bnxt_ulp_regfile_index field,
enum bnxt_ulp_rf_idx field,
uint64_t *data);
/*
@ -128,11 +128,11 @@ ulp_regfile_read(struct ulp_regfile *regfile,
* data [in] The value is written into this variable. It is going to be in the
* same byte order as it was written.
*
* returns zero on error
* returns zero on success
*/
uint32_t
int32_t
ulp_regfile_write(struct ulp_regfile *regfile,
enum bnxt_ulp_regfile_index field,
enum bnxt_ulp_rf_idx field,
uint64_t data);
/*