net/ixgbe: implement descriptor status API
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
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@ -42,6 +42,8 @@ Inner L3 checksum = Y
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Inner L4 checksum = Y
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Packet type parsing = Y
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Timesync = Y
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Rx descriptor status = Y
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Tx descriptor status = Y
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Basic stats = Y
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Extended stats = Y
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Stats per queue = Y
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@ -32,6 +32,8 @@ Flow control = Y
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Rate limitation = Y
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Traffic mirroring = Y
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Timesync = Y
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Rx descriptor status = Y
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Tx descriptor status = Y
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Basic stats = Y
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Extended stats = Y
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Stats per queue = Y
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@ -25,6 +25,8 @@ L4 checksum offload = Y
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Inner L3 checksum = Y
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Inner L4 checksum = Y
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Packet type parsing = Y
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Rx descriptor status = Y
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Tx descriptor status = Y
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Basic stats = Y
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Extended stats = Y
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Registers dump = Y
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@ -17,6 +17,8 @@ RSS hash = Y
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RSS key update = Y
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RSS reta update = Y
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VLAN filter = Y
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Rx descriptor status = Y
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Tx descriptor status = Y
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Basic stats = Y
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Extended stats = Y
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Registers dump = Y
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@ -554,6 +554,8 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
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.rx_queue_release = ixgbe_dev_rx_queue_release,
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.rx_queue_count = ixgbe_dev_rx_queue_count,
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.rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
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.rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
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.tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
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.tx_queue_setup = ixgbe_dev_tx_queue_setup,
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.tx_queue_release = ixgbe_dev_tx_queue_release,
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.dev_led_on = ixgbe_dev_led_on,
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@ -632,6 +634,8 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
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.rx_queue_setup = ixgbe_dev_rx_queue_setup,
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.rx_queue_release = ixgbe_dev_rx_queue_release,
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.rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
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.rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
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.tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
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.tx_queue_setup = ixgbe_dev_tx_queue_setup,
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.tx_queue_release = ixgbe_dev_tx_queue_release,
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.rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
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@ -516,6 +516,9 @@ uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
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int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
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int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
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int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
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int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
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int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
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void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
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@ -2945,6 +2945,63 @@ ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
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rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
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}
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int
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ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
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{
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struct ixgbe_rx_queue *rxq = rx_queue;
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volatile uint32_t *status;
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uint32_t nb_hold, desc;
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if (unlikely(offset >= rxq->nb_rx_desc))
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return -EINVAL;
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#ifdef RTE_IXGBE_INC_VECTOR
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if (rxq->rx_using_sse)
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nb_hold = rxq->rxrearm_nb;
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else
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#endif
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nb_hold = rxq->nb_rx_hold;
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if (offset >= rxq->nb_rx_desc - nb_hold)
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return RTE_ETH_RX_DESC_UNAVAIL;
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desc = rxq->rx_tail + offset;
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if (desc >= rxq->nb_rx_desc)
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desc -= rxq->nb_rx_desc;
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status = &rxq->rx_ring[desc].wb.upper.status_error;
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if (*status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))
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return RTE_ETH_RX_DESC_DONE;
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return RTE_ETH_RX_DESC_AVAIL;
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}
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int
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ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
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{
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struct ixgbe_tx_queue *txq = tx_queue;
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volatile uint32_t *status;
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uint32_t desc;
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if (unlikely(offset >= txq->nb_tx_desc))
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return -EINVAL;
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desc = txq->tx_tail + offset;
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/* go to next desc that has the RS bit */
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desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
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txq->tx_rs_thresh;
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if (desc >= txq->nb_tx_desc) {
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desc -= txq->nb_tx_desc;
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if (desc >= txq->nb_tx_desc)
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desc -= txq->nb_tx_desc;
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}
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status = &txq->tx_ring[desc].wb.status;
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if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
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return RTE_ETH_TX_DESC_DONE;
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return RTE_ETH_TX_DESC_FULL;
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}
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void __attribute__((cold))
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ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
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{
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