net/e1000: always enable receive and transmit
The transmit and receive controller state machines are only enabled after receiving an interrupt and the link status is now valid. If an adapter is being used in conjunction with NC-SI, network controller sideband interface, the adapter may never get a link state change interrupt since the adapter's PHY is always link up and never changes state. To fix this, always enable and disable the transmit and receive with .dev_start and .dev_stop. This is a better match for what is typically done with the other PMD's. Since we may never get an interrupt to check the link state, we also poll once at the end of .dev_start to get the current link status. Signed-off-by: Chas Williams <chas3@att.com> Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
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cde1f02528
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a2efa4f660
@ -560,6 +560,30 @@ em_set_pba(struct e1000_hw *hw)
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E1000_WRITE_REG(hw, E1000_PBA, pba);
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}
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static void
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eth_em_rxtx_control(struct rte_eth_dev *dev,
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bool enable)
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{
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t tctl, rctl;
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tctl = E1000_READ_REG(hw, E1000_TCTL);
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rctl = E1000_READ_REG(hw, E1000_RCTL);
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if (enable) {
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/* enable Tx/Rx */
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tctl |= E1000_TCTL_EN;
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rctl |= E1000_RCTL_EN;
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} else {
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/* disable Tx/Rx */
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tctl &= ~E1000_TCTL_EN;
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rctl &= ~E1000_RCTL_EN;
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}
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E1000_WRITE_REG(hw, E1000_TCTL, tctl);
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E1000_WRITE_REG(hw, E1000_RCTL, rctl);
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E1000_WRITE_FLUSH(hw);
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}
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static int
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eth_em_start(struct rte_eth_dev *dev)
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{
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@ -733,6 +757,9 @@ eth_em_start(struct rte_eth_dev *dev)
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adapter->stopped = 0;
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eth_em_rxtx_control(dev, true);
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eth_em_link_update(dev, 0);
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PMD_INIT_LOG(DEBUG, "<<");
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return 0;
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@ -758,6 +785,7 @@ eth_em_stop(struct rte_eth_dev *dev)
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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eth_em_rxtx_control(dev, false);
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em_rxq_intr_disable(hw);
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em_lsc_intr_disable(hw);
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@ -1584,7 +1612,6 @@ eth_em_interrupt_action(struct rte_eth_dev *dev,
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct e1000_interrupt *intr =
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E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
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uint32_t tctl, rctl;
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struct rte_eth_link link;
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int ret;
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@ -1616,21 +1643,6 @@ eth_em_interrupt_action(struct rte_eth_dev *dev,
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pci_dev->addr.domain, pci_dev->addr.bus,
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pci_dev->addr.devid, pci_dev->addr.function);
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tctl = E1000_READ_REG(hw, E1000_TCTL);
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rctl = E1000_READ_REG(hw, E1000_RCTL);
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if (link.link_status) {
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/* enable Tx/Rx */
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tctl |= E1000_TCTL_EN;
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rctl |= E1000_RCTL_EN;
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} else {
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/* disable Tx/Rx */
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tctl &= ~E1000_TCTL_EN;
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rctl &= ~E1000_RCTL_EN;
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}
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E1000_WRITE_REG(hw, E1000_TCTL, tctl);
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E1000_WRITE_REG(hw, E1000_RCTL, rctl);
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E1000_WRITE_FLUSH(hw);
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return 0;
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}
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@ -1277,6 +1277,31 @@ eth_igb_configure(struct rte_eth_dev *dev)
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return 0;
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}
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static void
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eth_igb_rxtx_control(struct rte_eth_dev *dev,
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bool enable)
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{
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t tctl, rctl;
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tctl = E1000_READ_REG(hw, E1000_TCTL);
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rctl = E1000_READ_REG(hw, E1000_RCTL);
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if (enable) {
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/* enable Tx/Rx */
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tctl |= E1000_TCTL_EN;
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rctl |= E1000_RCTL_EN;
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} else {
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/* disable Tx/Rx */
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tctl &= ~E1000_TCTL_EN;
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rctl &= ~E1000_RCTL_EN;
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}
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E1000_WRITE_REG(hw, E1000_TCTL, tctl);
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E1000_WRITE_REG(hw, E1000_RCTL, rctl);
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E1000_WRITE_FLUSH(hw);
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}
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static int
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eth_igb_start(struct rte_eth_dev *dev)
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{
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@ -1480,6 +1505,9 @@ eth_igb_start(struct rte_eth_dev *dev)
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/* restore all types filter */
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igb_filter_restore(dev);
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eth_igb_rxtx_control(dev, true);
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eth_igb_link_update(dev, 0);
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PMD_INIT_LOG(DEBUG, "<<");
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return 0;
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@ -1505,6 +1533,8 @@ eth_igb_stop(struct rte_eth_dev *dev)
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struct rte_eth_link link;
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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eth_igb_rxtx_control(dev, false);
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igb_intr_disable(hw);
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/* disable intr eventfd mapping */
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@ -2835,7 +2865,6 @@ eth_igb_interrupt_action(struct rte_eth_dev *dev,
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struct e1000_interrupt *intr =
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E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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uint32_t tctl, rctl;
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struct rte_eth_link link;
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int ret;
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@ -2877,20 +2906,6 @@ eth_igb_interrupt_action(struct rte_eth_dev *dev,
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pci_dev->addr.bus,
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pci_dev->addr.devid,
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pci_dev->addr.function);
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tctl = E1000_READ_REG(hw, E1000_TCTL);
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rctl = E1000_READ_REG(hw, E1000_RCTL);
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if (link.link_status) {
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/* enable Tx/Rx */
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tctl |= E1000_TCTL_EN;
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rctl |= E1000_RCTL_EN;
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} else {
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/* disable Tx/Rx */
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tctl &= ~E1000_TCTL_EN;
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rctl &= ~E1000_RCTL_EN;
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}
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E1000_WRITE_REG(hw, E1000_TCTL, tctl);
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E1000_WRITE_REG(hw, E1000_RCTL, rctl);
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E1000_WRITE_FLUSH(hw);
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_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
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NULL);
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}
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