vdpa/mlx5: add basic steering configurations
Add a steering object to be managed by a new file mlx5_vdpa_steer.c. Allow promiscuous flow to scatter the device Rx packets to the virtio queues using RSS action. In order to allow correct RSS in L3 and L4, split the flow to 7 flows as required by the device. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
This commit is contained in:
Matan Azrad
Ferruh Yigit
parent
2aa8444b00
commit
a5a1d98ddc
@ -11,6 +11,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa.c
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_mem.c
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_event.c
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_virtq.c
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_steer.c
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# Basic CFLAGS.
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CFLAGS += -O3
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@ -15,6 +15,7 @@ sources = files(
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'mlx5_vdpa_mem.c',
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'mlx5_vdpa_event.c',
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'mlx5_vdpa_virtq.c',
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'mlx5_vdpa_steer.c',
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)
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cflags_options = [
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'-std=c11',
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@ -209,6 +209,7 @@ mlx5_vdpa_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
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goto error;
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}
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priv->caps = attr.vdpa;
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priv->log_max_rqt_size = attr.log_max_rqt_size;
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}
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priv->ctx = ctx;
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priv->dev_addr.pci_addr = pci_dev->addr;
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@ -81,6 +81,18 @@ struct mlx5_vdpa_virtq {
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} umems[3];
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};
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struct mlx5_vdpa_steer {
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struct mlx5_devx_obj *rqt;
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void *domain;
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void *tbl;
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struct {
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struct mlx5dv_flow_matcher *matcher;
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struct mlx5_devx_obj *tir;
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void *tir_action;
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void *flow;
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} rss[7];
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};
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struct mlx5_vdpa_priv {
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TAILQ_ENTRY(mlx5_vdpa_priv) next;
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int id; /* vDPA device id. */
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@ -101,7 +113,9 @@ struct mlx5_vdpa_priv {
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struct mlx5_devx_obj *tis;
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uint16_t nr_virtqs;
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uint64_t features; /* Negotiated features. */
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uint16_t log_max_rqt_size;
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SLIST_HEAD(virtq_list, mlx5_vdpa_virtq) virtq_list;
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struct mlx5_vdpa_steer steer;
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SLIST_HEAD(mr_list, mlx5_vdpa_query_mr) mr_list;
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};
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@ -198,4 +212,24 @@ void mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv);
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*/
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int mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv);
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/**
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* Unset steering and release all its related resources- stop traffic.
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*
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* @param[in] priv
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* The vdpa driver private structure.
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*/
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int mlx5_vdpa_steer_unset(struct mlx5_vdpa_priv *priv);
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/**
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* Setup steering and all its related resources to enable RSS traffic from the
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* device to all the Rx host queues.
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*
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* @param[in] priv
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* The vdpa driver private structure.
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*
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* @return
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* 0 on success, a negative value otherwise.
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*/
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int mlx5_vdpa_steer_setup(struct mlx5_vdpa_priv *priv);
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#endif /* RTE_PMD_MLX5_VDPA_H_ */
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265
drivers/vdpa/mlx5/mlx5_vdpa_steer.c
Normal file
265
drivers/vdpa/mlx5/mlx5_vdpa_steer.c
Normal file
@ -0,0 +1,265 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2019 Mellanox Technologies, Ltd
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*/
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#include <netinet/in.h>
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#include <rte_malloc.h>
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#include <rte_errno.h>
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#include <rte_common.h>
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#include <mlx5_common.h>
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#include "mlx5_vdpa_utils.h"
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#include "mlx5_vdpa.h"
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int
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mlx5_vdpa_steer_unset(struct mlx5_vdpa_priv *priv)
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{
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int ret __rte_unused;
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unsigned i;
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for (i = 0; i < RTE_DIM(priv->steer.rss); ++i) {
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if (priv->steer.rss[i].flow) {
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claim_zero(mlx5_glue->dv_destroy_flow
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(priv->steer.rss[i].flow));
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priv->steer.rss[i].flow = NULL;
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}
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if (priv->steer.rss[i].tir_action) {
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claim_zero(mlx5_glue->destroy_flow_action
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(priv->steer.rss[i].tir_action));
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priv->steer.rss[i].tir_action = NULL;
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}
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if (priv->steer.rss[i].tir) {
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claim_zero(mlx5_devx_cmd_destroy
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(priv->steer.rss[i].tir));
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priv->steer.rss[i].tir = NULL;
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}
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if (priv->steer.rss[i].matcher) {
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claim_zero(mlx5_glue->dv_destroy_flow_matcher
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(priv->steer.rss[i].matcher));
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priv->steer.rss[i].matcher = NULL;
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}
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}
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if (priv->steer.tbl) {
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claim_zero(mlx5_glue->dr_destroy_flow_tbl(priv->steer.tbl));
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priv->steer.tbl = NULL;
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}
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if (priv->steer.domain) {
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claim_zero(mlx5_glue->dr_destroy_domain(priv->steer.domain));
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priv->steer.domain = NULL;
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}
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if (priv->steer.rqt) {
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claim_zero(mlx5_devx_cmd_destroy(priv->steer.rqt));
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priv->steer.rqt = NULL;
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}
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return 0;
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}
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/*
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* According to VIRTIO_NET Spec the virtqueues index identity its type by:
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* 0 receiveq1
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* 1 transmitq1
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* ...
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* 2(N-1) receiveqN
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* 2(N-1)+1 transmitqN
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* 2N controlq
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*/
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static uint8_t
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is_virtq_recvq(int virtq_index, int nr_vring)
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{
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if (virtq_index % 2 == 0 && virtq_index != nr_vring - 1)
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return 1;
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return 0;
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}
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#define MLX5_VDPA_DEFAULT_RQT_SIZE 512
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static int __rte_unused
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mlx5_vdpa_rqt_prepare(struct mlx5_vdpa_priv *priv)
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{
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struct mlx5_vdpa_virtq *virtq;
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uint32_t rqt_n = RTE_MIN(MLX5_VDPA_DEFAULT_RQT_SIZE,
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1 << priv->log_max_rqt_size);
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struct mlx5_devx_rqt_attr *attr = rte_zmalloc(__func__, sizeof(*attr)
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+ rqt_n *
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sizeof(uint32_t), 0);
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uint32_t i = 0, j;
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int ret = 0;
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if (!attr) {
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DRV_LOG(ERR, "Failed to allocate RQT attributes memory.");
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rte_errno = ENOMEM;
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return -ENOMEM;
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}
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SLIST_FOREACH(virtq, &priv->virtq_list, next) {
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if (is_virtq_recvq(virtq->index, priv->nr_virtqs)) {
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attr->rq_list[i] = virtq->virtq->id;
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i++;
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}
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}
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for (j = 0; i != rqt_n; ++i, ++j)
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attr->rq_list[i] = attr->rq_list[j];
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attr->rq_type = MLX5_INLINE_Q_TYPE_VIRTQ;
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attr->rqt_max_size = rqt_n;
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attr->rqt_actual_size = rqt_n;
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if (!priv->steer.rqt) {
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priv->steer.rqt = mlx5_devx_cmd_create_rqt(priv->ctx, attr);
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if (!priv->steer.rqt) {
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DRV_LOG(ERR, "Failed to create RQT.");
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ret = -rte_errno;
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}
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} else {
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ret = mlx5_devx_cmd_modify_rqt(priv->steer.rqt, attr);
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if (ret)
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DRV_LOG(ERR, "Failed to modify RQT.");
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}
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rte_free(attr);
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return ret;
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}
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static int __rte_unused
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mlx5_vdpa_rss_flows_create(struct mlx5_vdpa_priv *priv)
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{
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#ifdef HAVE_MLX5DV_DR
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struct mlx5_devx_tir_attr tir_att = {
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.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT,
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.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ,
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.transport_domain = priv->td->id,
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.indirect_table = priv->steer.rqt->id,
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.rx_hash_symmetric = 1,
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.rx_hash_toeplitz_key = { 0x2cc681d1, 0x5bdbf4f7, 0xfca28319,
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0xdb1a3e94, 0x6b9e38d9, 0x2c9c03d1,
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0xad9944a7, 0xd9563d59, 0x063c25f3,
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0xfc1fdc2a },
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};
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struct {
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size_t size;
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/**< Size of match value. Do NOT split size and key! */
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uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
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/**< Matcher value. This value is used as the mask or a key. */
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} matcher_mask = {
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.size = sizeof(matcher_mask.buf),
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},
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matcher_value = {
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.size = sizeof(matcher_value.buf),
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};
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struct mlx5dv_flow_matcher_attr dv_attr = {
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.type = IBV_FLOW_ATTR_NORMAL,
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.match_mask = (void *)&matcher_mask,
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};
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void *match_m = matcher_mask.buf;
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void *match_v = matcher_value.buf;
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void *headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers);
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void *headers_v = MLX5_ADDR_OF(fte_match_param, match_v, outer_headers);
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void *actions[1];
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const uint8_t l3_hash =
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(1 << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
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(1 << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP);
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const uint8_t l4_hash =
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(1 << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT) |
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(1 << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT);
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enum { PRIO, CRITERIA, IP_VER_M, IP_VER_V, IP_PROT_M, IP_PROT_V, L3_BIT,
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L4_BIT, HASH, END};
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const uint8_t vars[RTE_DIM(priv->steer.rss)][END] = {
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{ 7, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 6, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 4, 0, 0,
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MLX5_L3_PROT_TYPE_IPV4, 0, l3_hash },
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{ 6, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 6, 0, 0,
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MLX5_L3_PROT_TYPE_IPV6, 0, l3_hash },
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{ 5, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 4, 0xff,
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IPPROTO_UDP, MLX5_L3_PROT_TYPE_IPV4, MLX5_L4_PROT_TYPE_UDP,
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l3_hash | l4_hash },
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{ 5, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 4, 0xff,
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IPPROTO_TCP, MLX5_L3_PROT_TYPE_IPV4, MLX5_L4_PROT_TYPE_TCP,
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l3_hash | l4_hash },
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{ 5, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 6, 0xff,
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IPPROTO_UDP, MLX5_L3_PROT_TYPE_IPV6, MLX5_L4_PROT_TYPE_UDP,
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l3_hash | l4_hash },
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{ 5, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 6, 0xff,
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IPPROTO_TCP, MLX5_L3_PROT_TYPE_IPV6, MLX5_L4_PROT_TYPE_TCP,
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l3_hash | l4_hash },
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};
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unsigned i;
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for (i = 0; i < RTE_DIM(priv->steer.rss); ++i) {
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dv_attr.priority = vars[i][PRIO];
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dv_attr.match_criteria_enable = vars[i][CRITERIA];
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MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
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vars[i][IP_VER_M]);
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MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
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vars[i][IP_VER_V]);
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MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
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vars[i][IP_PROT_M]);
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MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
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vars[i][IP_PROT_V]);
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tir_att.rx_hash_field_selector_outer.l3_prot_type =
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vars[i][L3_BIT];
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tir_att.rx_hash_field_selector_outer.l4_prot_type =
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vars[i][L4_BIT];
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tir_att.rx_hash_field_selector_outer.selected_fields =
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vars[i][HASH];
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priv->steer.rss[i].matcher = mlx5_glue->dv_create_flow_matcher
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(priv->ctx, &dv_attr, priv->steer.tbl);
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if (!priv->steer.rss[i].matcher) {
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DRV_LOG(ERR, "Failed to create matcher %d.", i);
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goto error;
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}
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priv->steer.rss[i].tir = mlx5_devx_cmd_create_tir(priv->ctx,
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&tir_att);
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if (!priv->steer.rss[i].tir) {
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DRV_LOG(ERR, "Failed to create TIR %d.", i);
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goto error;
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}
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priv->steer.rss[i].tir_action =
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mlx5_glue->dv_create_flow_action_dest_devx_tir
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(priv->steer.rss[i].tir->obj);
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if (!priv->steer.rss[i].tir_action) {
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DRV_LOG(ERR, "Failed to create TIR action %d.", i);
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goto error;
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}
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actions[0] = priv->steer.rss[i].tir_action;
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priv->steer.rss[i].flow = mlx5_glue->dv_create_flow
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(priv->steer.rss[i].matcher,
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(void *)&matcher_value, 1, actions);
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if (!priv->steer.rss[i].flow) {
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DRV_LOG(ERR, "Failed to create flow %d.", i);
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goto error;
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}
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}
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return 0;
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error:
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/* Resources will be freed by the caller. */
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return -1;
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#else
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(void)priv;
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return -ENOTSUP;
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#endif /* HAVE_MLX5DV_DR */
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}
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int
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mlx5_vdpa_steer_setup(struct mlx5_vdpa_priv *priv)
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{
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#ifdef HAVE_MLX5DV_DR
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if (mlx5_vdpa_rqt_prepare(priv))
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return -1;
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priv->steer.domain = mlx5_glue->dr_create_domain(priv->ctx,
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MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
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if (!priv->steer.domain) {
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DRV_LOG(ERR, "Failed to create Rx domain.");
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goto error;
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}
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priv->steer.tbl = mlx5_glue->dr_create_flow_tbl(priv->steer.domain, 0);
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if (!priv->steer.tbl) {
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DRV_LOG(ERR, "Failed to create table 0 with Rx domain.");
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goto error;
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}
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if (mlx5_vdpa_rss_flows_create(priv))
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goto error;
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return 0;
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error:
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mlx5_vdpa_steer_unset(priv);
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return -1;
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#else
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(void)priv;
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return -ENOTSUP;
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#endif /* HAVE_MLX5DV_DR */
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}
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