d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

event/cnxk: add options for timer chunk size and rings

Browse Source 
Add devargs to control default chunk size and max numbers of
timer rings to attach to a given RVU PF.

Example:
	--dev "0002:1e:00.0,tim_chnk_slots=1024"
	--dev "0002:1e:00.0,tim_rings_lmt=4"

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
This commit is contained in:
Shijith Thotton 2021-05-04 05:57:18 +05:30 committed by Jerin Jacob
parent 9891f76b60
commit a66fa85668
5 changed files with 46 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
doc/guides/eventdevs/cnxk.rst
View File

@ -103,6 +103,29 @@ Runtime Config Options
-a 0002:0e:00.0,tim_disable_npa=1
- ``TIM modify chunk slots``
The ``tim_chnk_slots`` devargs can be used to modify number of chunk slots.
Chunks are used to store event timers, a chunk can be visualised as an array
where the last element points to the next chunk and rest of them are used to
store events. TIM traverses the list of chunks and enqueues the event timers
to SSO. The default value is 255 and the max value is 4095.
For example::
-a 0002:0e:00.0,tim_chnk_slots=1023
- ``TIM limit max rings reserved``
The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM
rings i.e. event timer adapter reserved on probe. Since, TIM rings are HW
resources we can avoid starving other applications by not grabbing all the
rings.
For example::
-a 0002:0e:00.0,tim_rings_lmt=5
Debugging Options
-----------------

4
drivers/event/cnxk/cn10k_eventdev.c
View File

@ -503,4 +503,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
CNXK_SSO_GGRP_QOS "=<string>"
CN10K_SSO_GW_MODE "=<int>"
CNXK_TIM_DISABLE_NPA "=1");
CNXK_TIM_DISABLE_NPA "=1"
CNXK_TIM_CHNK_SLOTS "=<int>"
CNXK_TIM_RINGS_LMT "=<int>");

4
drivers/event/cnxk/cn9k_eventdev.c
View File

@ -572,4 +572,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
CNXK_SSO_GGRP_QOS "=<string>"
CN9K_SSO_SINGLE_WS "=1"
CNXK_TIM_DISABLE_NPA "=1");
CNXK_TIM_DISABLE_NPA "=1"
CNXK_TIM_CHNK_SLOTS "=<int>"
CNXK_TIM_RINGS_LMT "=<int>");

14
drivers/event/cnxk/cnxk_tim_evdev.c
View File

@ -253,6 +253,10 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)
rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,
&dev->disable_npa);
rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,
&dev->chunk_slots);
rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,
&dev->min_ring_cnt);
rte_kvargs_free(kvlist);
}
@ -278,6 +282,7 @@ cnxk_tim_init(struct roc_sso *sso)
cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);
dev->tim.roc_sso = sso;
dev->tim.nb_lfs = dev->min_ring_cnt;
rc = roc_tim_init(&dev->tim);
if (rc < 0) {
plt_err("Failed to initialize roc tim resources");
@ -285,7 +290,14 @@ cnxk_tim_init(struct roc_sso *sso)
return;
}
dev->nb_rings = rc;
dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS &&
dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) {
dev->chunk_sz =
(dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT;
} else {
dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
}
}
void

4
drivers/event/cnxk/cnxk_tim_evdev.h
View File

@ -34,6 +34,8 @@
#define CN9K_TIM_MIN_TMO_TKS (256)
#define CNXK_TIM_DISABLE_NPA "tim_disable_npa"
#define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots"
#define CNXK_TIM_RINGS_LMT "tim_rings_lmt"
struct cnxk_tim_evdev {
struct roc_tim tim;
@ -42,6 +44,8 @@ struct cnxk_tim_evdev {
uint32_t chunk_sz;
/* Dev args */
uint8_t disable_npa;
uint16_t chunk_slots;
uint16_t min_ring_cnt;
};
enum cnxk_tim_clk_src {