net/octeontx: add application domain validation
Add domain validation for PKI and PKO vfs Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
This commit is contained in:
parent
b4134b2d31
commit
a6d6f0afd0
@ -35,6 +35,7 @@ struct mbox {
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uint8_t *ram_mbox_base; /* Base address of mbox message stored in ram */
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uint8_t *reg; /* Store to this register triggers PF mbox interrupt */
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uint16_t tag_own; /* Last tag which was written to own channel */
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uint16_t domain; /* Domain */
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rte_spinlock_t lock;
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};
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@ -198,7 +199,7 @@ mbox_send(struct mbox *m, struct octeontx_mbox_hdr *hdr, const void *txmsg,
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}
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int
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octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base)
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octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base, uint16_t domain)
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{
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struct mbox *m = &octeontx_mbox;
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@ -215,13 +216,14 @@ octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base)
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if (m->reg != NULL) {
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rte_spinlock_init(&m->lock);
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m->init_once = 1;
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m->domain = domain;
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}
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return 0;
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}
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int
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octeontx_mbox_set_reg(uint8_t *reg)
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octeontx_mbox_set_reg(uint8_t *reg, uint16_t domain)
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{
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struct mbox *m = &octeontx_mbox;
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@ -238,6 +240,7 @@ octeontx_mbox_set_reg(uint8_t *reg)
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if (m->ram_mbox_base != NULL) {
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rte_spinlock_init(&m->lock);
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m->init_once = 1;
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m->domain = domain;
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}
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return 0;
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@ -344,3 +347,11 @@ octeontx_mbox_init(void)
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return 0;
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}
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uint16_t
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octeontx_get_global_domain(void)
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{
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struct mbox *m = &octeontx_mbox;
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return m->domain;
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}
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@ -36,8 +36,10 @@ struct octeontx_mbox_hdr {
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};
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int octeontx_mbox_init(void);
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int octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base);
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int octeontx_mbox_set_reg(uint8_t *reg);
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void octeontx_set_global_domain(uint16_t global_domain);
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uint16_t octeontx_get_global_domain(void);
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int octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base, uint16_t domain);
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int octeontx_mbox_set_reg(uint8_t *reg, uint16_t domain);
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int octeontx_mbox_send(struct octeontx_mbox_hdr *hdr,
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void *txdata, uint16_t txlen, void *rxdata, uint16_t rxlen);
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@ -1,6 +1,7 @@
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DPDK_20.0 {
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global:
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octeontx_get_global_domain;
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octeontx_logtype_mbox;
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octeontx_mbox_init;
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octeontx_mbox_send;
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@ -181,7 +181,8 @@ ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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sdev.total_ssowvfs++;
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if (vfid == 0) {
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ram_mbox_base = ssovf_bar(OCTEONTX_SSO_HWS, 0, 4);
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if (octeontx_mbox_set_ram_mbox_base(ram_mbox_base)) {
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if (octeontx_mbox_set_ram_mbox_base(ram_mbox_base,
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res->domain)) {
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mbox_log_err("Invalid Failed to set ram mbox base");
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return -EINVAL;
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}
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@ -257,7 +258,7 @@ ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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if (vfid == 0) {
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reg = ssovf_bar(OCTEONTX_SSO_GROUP, 0, 0);
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reg += SSO_VHGRP_PF_MBOX(1);
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if (octeontx_mbox_set_reg(reg)) {
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if (octeontx_mbox_set_reg(reg, res->domain)) {
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mbox_log_err("Invalid Failed to set mbox_reg");
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return -EINVAL;
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}
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@ -7,19 +7,50 @@
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#include <rte_eal.h>
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#include <rte_bus_pci.h>
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#include "../octeontx_logs.h"
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#include "octeontx_io.h"
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#include "octeontx_pkivf.h"
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struct octeontx_pkivf {
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uint8_t *bar0;
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uint8_t status;
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uint16_t domain;
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uint16_t vfid;
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};
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struct octeontx_pki_vf_ctl_s {
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struct octeontx_pkivf pki[PKI_VF_MAX];
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};
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static struct octeontx_pki_vf_ctl_s pki_vf_ctl;
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int
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octeontx_pki_port_open(int port)
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{
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uint16_t global_domain = octeontx_get_global_domain();
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struct octeontx_mbox_hdr hdr;
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int res;
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mbox_pki_port_t port_type = {
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.port_type = OCTTX_PORT_TYPE_NET,
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};
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int i, res;
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/* Check if atleast one PKI vf is in application domain. */
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for (i = 0; i < PKI_VF_MAX; i++) {
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if (pki_vf_ctl.pki[i].domain != global_domain)
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continue;
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break;
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}
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if (i == PKI_VF_MAX)
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return -ENODEV;
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hdr.coproc = OCTEONTX_PKI_COPROC;
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hdr.msg = MBOX_PKI_PORT_OPEN;
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hdr.vfid = port;
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res = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);
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res = octeontx_mbox_send(&hdr, &port_type, sizeof(mbox_pki_port_t),
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NULL, 0);
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if (res < 0)
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return -EACCES;
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return res;
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@ -113,13 +144,40 @@ octeontx_pki_port_errchk_config(int port, pki_errchk_cfg_t *cfg)
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static int
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pkivf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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{
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RTE_SET_USED(pci_drv);
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RTE_SET_USED(pci_dev);
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struct octeontx_pkivf *res;
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static uint8_t vf_cnt;
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uint16_t domain;
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uint16_t vfid;
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uint8_t *bar0;
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uint64_t val;
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RTE_SET_USED(pci_drv);
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/* For secondary processes, the primary has done all the work */
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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return 0;
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if (pci_dev->mem_resource[0].addr == NULL) {
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octeontx_log_err("PKI Empty bar[0] %p",
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pci_dev->mem_resource[0].addr);
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return -ENODEV;
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}
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bar0 = pci_dev->mem_resource[0].addr;
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val = octeontx_read64(bar0);
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domain = val & 0xffff;
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vfid = (val >> 16) & 0xffff;
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if (unlikely(vfid >= PKI_VF_MAX)) {
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octeontx_log_err("pki: Invalid vfid %d", vfid);
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return -EINVAL;
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}
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res = &pki_vf_ctl.pki[vf_cnt++];
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res->vfid = vfid;
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res->domain = domain;
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res->bar0 = bar0;
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octeontx_log_dbg("PKI Domain=%d vfid=%d", res->domain, res->vfid);
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return 0;
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}
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@ -48,6 +48,10 @@ enum {
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MBOX_PKI_PARSE_NOTHING = 0x7f
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};
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/* PKI maximum constants */
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#define PKI_VF_MAX (32)
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#define PKI_MAX_PKTLEN (32768)
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/* Interface types: */
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enum {
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OCTTX_PORT_TYPE_NET, /* Network interface ports */
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@ -231,10 +235,6 @@ typedef struct mbox_pki_port_delete_qos_entry {
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uint16_t index;
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} mbox_pki_del_qos_t;
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/* PKI maximum constants */
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#define PKI_VF_MAX (1)
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#define PKI_MAX_PKTLEN (32768)
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/* pki pkind parse mode */
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enum {
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PKI_PARSE_LA_TO_LG = 0,
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@ -24,6 +24,8 @@ struct octeontx_pko_iomem {
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};
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#define PKO_IOMEM_NULL (struct octeontx_pko_iomem){0, 0, 0}
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#define PKO_VALID 0x1
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#define PKO_INUSE 0x2
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struct octeontx_pko_fc_ctl_s {
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int64_t buf_cnt;
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@ -33,13 +35,14 @@ struct octeontx_pko_fc_ctl_s {
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struct octeontx_pkovf {
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uint8_t *bar0;
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uint8_t *bar2;
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uint8_t status;
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uint16_t domain;
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uint16_t vfid;
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};
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struct octeontx_pko_vf_ctl_s {
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rte_spinlock_t lock;
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uint16_t global_domain;
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struct octeontx_pko_iomem fc_iomem;
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struct octeontx_pko_fc_ctl_s *fc_ctl;
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struct octeontx_pkovf pko[PKO_VF_MAX];
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@ -403,7 +406,7 @@ octeontx_pko_channel_query(struct octeontx_pko_vf_ctl_s *ctl, uint64_t chanid,
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curr.lmtline_va = ctl->pko[dq_vf].bar2;
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curr.ioreg_va = (void *)((uintptr_t)ctl->pko[dq_vf].bar0
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+ PKO_VF_DQ_OP_SEND((dq), 0));
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curr.fc_status_va = ctl->fc_ctl + dq;
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curr.fc_status_va = ctl->fc_ctl + dq_num;
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octeontx_log_dbg("lmtline=%p ioreg_va=%p fc_status_va=%p",
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curr.lmtline_va, curr.ioreg_va,
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@ -431,8 +434,10 @@ octeontx_pko_channel_query_dqs(int chanid, void *out, size_t out_elem_size,
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int
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octeontx_pko_vf_count(void)
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{
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uint16_t global_domain = octeontx_get_global_domain();
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int vf_cnt;
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pko_vf_ctl.global_domain = global_domain;
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vf_cnt = 0;
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while (pko_vf_ctl.pko[vf_cnt].bar0)
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vf_cnt++;
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@ -440,6 +445,26 @@ octeontx_pko_vf_count(void)
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return vf_cnt;
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}
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size_t
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octeontx_pko_get_vfid(void)
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{
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size_t vf_cnt = octeontx_pko_vf_count();
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size_t vf_idx;
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for (vf_idx = 0; vf_idx < vf_cnt; vf_idx++) {
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if (!(pko_vf_ctl.pko[vf_idx].status & PKO_VALID))
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continue;
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if (pko_vf_ctl.pko[vf_idx].status & PKO_INUSE)
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continue;
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pko_vf_ctl.pko[vf_idx].status |= PKO_INUSE;
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return pko_vf_ctl.pko[vf_idx].vfid;
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}
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return SIZE_MAX;
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}
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int
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octeontx_pko_init_fc(const size_t pko_vf_count)
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{
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@ -467,8 +492,10 @@ octeontx_pko_init_fc(const size_t pko_vf_count)
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/* Configure Flow-Control feature for all DQs of open VFs */
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for (vf_idx = 0; vf_idx < pko_vf_count; vf_idx++) {
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dq_ix = vf_idx * PKO_VF_NUM_DQ;
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if (pko_vf_ctl.pko[vf_idx].domain != pko_vf_ctl.global_domain)
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continue;
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dq_ix = pko_vf_ctl.pko[vf_idx].vfid * PKO_VF_NUM_DQ;
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vf_bar0 = pko_vf_ctl.pko[vf_idx].bar0;
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reg = (pko_vf_ctl.fc_iomem.iova +
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@ -479,6 +506,7 @@ octeontx_pko_init_fc(const size_t pko_vf_count)
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(0x1 << 0); /* ENABLE */
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octeontx_write64(reg, vf_bar0 + PKO_VF_DQ_FC_CONFIG);
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pko_vf_ctl.pko[vf_idx].status = PKO_VALID;
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octeontx_log_dbg("PKO: bar0 %p VF_idx %d DQ_FC_CFG=%" PRIx64 "",
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vf_bar0, (int)vf_idx, reg);
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@ -528,6 +556,7 @@ pkovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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uint16_t domain;
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uint8_t *bar0;
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uint8_t *bar2;
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static uint8_t vf_cnt;
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struct octeontx_pkovf *res;
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RTE_SET_USED(pci_drv);
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@ -558,7 +587,7 @@ pkovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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return -EINVAL;
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}
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res = &pko_vf_ctl.pko[vfid];
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res = &pko_vf_ctl.pko[vf_cnt++];
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res->vfid = vfid;
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res->domain = domain;
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res->bar0 = bar0;
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@ -5,6 +5,8 @@
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#ifndef __OCTEONTX_PKO_H__
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#define __OCTEONTX_PKO_H__
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#include <octeontx_mbox.h>
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/* PKO maximum constants */
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#define PKO_VF_MAX (32)
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#define PKO_VF_NUM_DQ (8)
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@ -63,6 +65,7 @@ int octeontx_pko_channel_close(int chanid);
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int octeontx_pko_channel_start(int chanid);
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int octeontx_pko_channel_stop(int chanid);
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int octeontx_pko_vf_count(void);
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size_t octeontx_pko_get_vfid(void);
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int octeontx_pko_init_fc(const size_t pko_vf_count);
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void octeontx_pko_fc_free(void);
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@ -308,7 +308,7 @@ octeontx_dev_configure(struct rte_eth_dev *dev)
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nic->num_tx_queues = dev->data->nb_tx_queues;
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ret = octeontx_pko_channel_open(nic->port_id * PKO_VF_NUM_DQ,
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ret = octeontx_pko_channel_open(nic->pko_vfid * PKO_VF_NUM_DQ,
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nic->num_tx_queues,
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nic->base_ochan);
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if (ret) {
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@ -719,7 +719,7 @@ octeontx_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
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RTE_SET_USED(nb_desc);
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RTE_SET_USED(socket_id);
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dq_num = (nic->port_id * PKO_VF_NUM_DQ) + qidx;
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dq_num = (nic->pko_vfid * PKO_VF_NUM_DQ) + qidx;
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/* Socket id check */
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if (socket_id != (unsigned int)SOCKET_ID_ANY &&
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@ -1001,6 +1001,7 @@ octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev,
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int socket_id)
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{
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int res;
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size_t pko_vfid;
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char octtx_name[OCTEONTX_MAX_NAME_LEN];
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struct octeontx_nic *nic = NULL;
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struct rte_eth_dev *eth_dev = NULL;
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@ -1039,7 +1040,15 @@ octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev,
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goto err;
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}
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data->dev_private = nic;
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pko_vfid = octeontx_pko_get_vfid();
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if (pko_vfid == SIZE_MAX) {
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octeontx_log_err("failed to get pko vfid");
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res = -ENODEV;
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goto err;
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}
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nic->pko_vfid = pko_vfid;
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nic->port_id = port;
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nic->evdev = evdev;
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@ -58,6 +58,7 @@ struct octeontx_nic {
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uint8_t mcast_mode;
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uint16_t num_tx_queues;
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uint64_t hwcap;
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uint8_t pko_vfid;
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uint8_t link_up;
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uint8_t duplex;
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uint8_t speed;
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