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crypto/dpaa2_sec: support DES-CBC

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add DES-CBC support for cipher_only, chain and ipsec protocol.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
This commit is contained in:
Akhil Goyal 2020-09-03 22:03:07 +05:30
parent 1fb9115a80
commit a6e892f427
4 changed files with 46 additions and 9 deletions
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3
doc/guides/cryptodevs/features/dpaa2_sec.ini
View File

@ -24,6 +24,7 @@ AES CBC (256) = Y
AES CTR (128) = Y
AES CTR (192) = Y
AES CTR (256) = Y
DES CBC = Y
3DES CBC = Y
SNOW3G UEA2 = Y
ZUC EEA3 = Y
@ -52,4 +53,4 @@ AES GCM (256) = Y
;
; Supported Asymmetric algorithms of the 'dpaa2_sec' crypto driver.
;
[Asymmetric]
[Asymmetric]

4
doc/guides/rel_notes/release_20_11.rst
View File

@ -164,6 +164,10 @@ New Features
Added a symmetric crypto PMD for Broadcom FlexSparc crypto units.
See :doc:`../cryptodevs/bcmfs` guide for more details on this new PMD.
* **Updated DPAA2_SEC crypto PMD.**
* Added DES-CBC support for cipher_only, chain and ipsec protocol.
* **Updated Marvell NITROX symmetric crypto PMD.**
* Added AES-GCM support.

26
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
View File

@ -1878,19 +1878,19 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
session->iv.length,
session->dir);
break;
case RTE_CRYPTO_CIPHER_AES_CTR:
cipherdata.algtype = OP_ALG_ALGSEL_AES;
cipherdata.algmode = OP_ALG_AAI_CTR;
session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CTR;
case RTE_CRYPTO_CIPHER_DES_CBC:
cipherdata.algtype = OP_ALG_ALGSEL_DES;
cipherdata.algmode = OP_ALG_AAI_CBC;
session->cipher_alg = RTE_CRYPTO_CIPHER_DES_CBC;
bufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0,
SHR_NEVER, &cipherdata,
session->iv.length,
session->dir);
break;
case RTE_CRYPTO_CIPHER_3DES_CTR:
cipherdata.algtype = OP_ALG_ALGSEL_3DES;
case RTE_CRYPTO_CIPHER_AES_CTR:
cipherdata.algtype = OP_ALG_ALGSEL_AES;
cipherdata.algmode = OP_ALG_AAI_CTR;
session->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CTR;
session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CTR;
bufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0,
SHR_NEVER, &cipherdata,
session->iv.length,
@ -1914,6 +1914,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
case RTE_CRYPTO_CIPHER_AES_F8:
case RTE_CRYPTO_CIPHER_AES_ECB:
case RTE_CRYPTO_CIPHER_3DES_ECB:
case RTE_CRYPTO_CIPHER_3DES_CTR:
case RTE_CRYPTO_CIPHER_AES_XTS:
case RTE_CRYPTO_CIPHER_ARC4:
case RTE_CRYPTO_CIPHER_NULL:
@ -2391,6 +2392,11 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
cipherdata.algmode = OP_ALG_AAI_CBC;
session->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CBC;
break;
case RTE_CRYPTO_CIPHER_DES_CBC:
cipherdata.algtype = OP_ALG_ALGSEL_DES;
cipherdata.algmode = OP_ALG_AAI_CBC;
session->cipher_alg = RTE_CRYPTO_CIPHER_DES_CBC;
break;
case RTE_CRYPTO_CIPHER_AES_CTR:
cipherdata.algtype = OP_ALG_ALGSEL_AES;
cipherdata.algmode = OP_ALG_AAI_CTR;
@ -2400,6 +2406,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
case RTE_CRYPTO_CIPHER_ZUC_EEA3:
case RTE_CRYPTO_CIPHER_NULL:
case RTE_CRYPTO_CIPHER_3DES_ECB:
case RTE_CRYPTO_CIPHER_3DES_CTR:
case RTE_CRYPTO_CIPHER_AES_ECB:
case RTE_CRYPTO_CIPHER_KASUMI_F8:
DPAA2_SEC_ERR("Crypto: Unsupported Cipher alg %u",
@ -2731,6 +2738,10 @@ dpaa2_sec_ipsec_proto_init(struct rte_crypto_cipher_xform *cipher_xform,
cipherdata->algtype = OP_PCL_IPSEC_3DES;
cipherdata->algmode = OP_ALG_AAI_CBC;
break;
case RTE_CRYPTO_CIPHER_DES_CBC:
cipherdata->algtype = OP_PCL_IPSEC_DES;
cipherdata->algmode = OP_ALG_AAI_CBC;
break;
case RTE_CRYPTO_CIPHER_AES_CTR:
cipherdata->algtype = OP_PCL_IPSEC_AES_CTR;
cipherdata->algmode = OP_ALG_AAI_CTR;
@ -2741,6 +2752,7 @@ dpaa2_sec_ipsec_proto_init(struct rte_crypto_cipher_xform *cipher_xform,
case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
case RTE_CRYPTO_CIPHER_ZUC_EEA3:
case RTE_CRYPTO_CIPHER_3DES_ECB:
case RTE_CRYPTO_CIPHER_3DES_CTR:
case RTE_CRYPTO_CIPHER_AES_ECB:
case RTE_CRYPTO_CIPHER_KASUMI_F8:
DPAA2_SEC_ERR("Crypto: Unsupported Cipher alg %u",

22
drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
* Copyright 2016 NXP
* Copyright 2016,2020 NXP
*
*/
@ -437,6 +437,26 @@ static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = {
}, }
}, }
},
{ /* DES CBC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
{.cipher = {
.algo = RTE_CRYPTO_CIPHER_DES_CBC,
.block_size = 8,
.key_size = {
.min = 8,
.max = 8,
.increment = 0
},
.iv_size = {
.min = 8,
.max = 8,
.increment = 0
}
}, }
}, }
},
{ /* 3DES CBC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {