crypto/mlx5: introduce Mellanox crypto driver
Add a new PMD for Mellanox devices- crypto PMD. The crypto PMD will be supported starting Nvidia ConnectX6 and BlueField2. The crypto PMD will add the support of encryption and decryption using the AES-XTS symmetric algorithm. The crypto PMD requires rdma-core and uses mlx5 DevX. This patch adds the PCI probing, basic functions, build files and log utility. Signed-off-by: Shiri Kuzin <shirik@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
This commit is contained in:
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@ -1102,6 +1102,12 @@ F: drivers/crypto/octeontx2/
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F: doc/guides/cryptodevs/octeontx2.rst
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F: doc/guides/cryptodevs/features/octeontx2.ini
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Mellanox mlx5
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M: Matan Azrad <matan@nvidia.com>
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F: drivers/crypto/mlx5/
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F: doc/guides/cryptodevs/mlx5.rst
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F: doc/guides/cryptodevs/features/mlx5.ini
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Null Crypto
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M: Declan Doherty <declan.doherty@intel.com>
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F: drivers/crypto/null/
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27
doc/guides/cryptodevs/features/mlx5.ini
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27
doc/guides/cryptodevs/features/mlx5.ini
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@ -0,0 +1,27 @@
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;
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; Features of a mlx5 crypto driver.
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;
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; Refer to default.ini for the full list of available PMD features.
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;
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[Features]
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HW Accelerated = Y
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;
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; Supported crypto algorithms of a mlx5 crypto driver.
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;
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[Cipher]
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;
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; Supported authentication algorithms of a mlx5 crypto driver.
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;
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[Auth]
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;
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; Supported AEAD algorithms of a mlx5 crypto driver.
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;
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[AEAD]
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;
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; Supported Asymmetric algorithms of a mlx5 crypto driver.
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;
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[Asymmetric]
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@ -23,6 +23,7 @@ Crypto Device Drivers
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octeontx
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octeontx2
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openssl
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mlx5
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mvsam
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nitrox
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null
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65
doc/guides/cryptodevs/mlx5.rst
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65
doc/guides/cryptodevs/mlx5.rst
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@ -0,0 +1,65 @@
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.. SPDX-License-Identifier: BSD-3-Clause
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Copyright (c) 2021 NVIDIA Corporation & Affiliates
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.. include:: <isonum.txt>
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MLX5 Crypto Driver
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==================
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The MLX5 crypto driver library
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(**librte_crypto_mlx5**) provides support for **Mellanox ConnectX-6**
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family adapters.
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Overview
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--------
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The device can provide disk encryption services,
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allowing data encryption and decryption towards a disk.
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Having all encryption/decryption operations done in a single device
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can reduce cost and overheads of the related FIPS certification,
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as ConnectX-6 is FIPS 140-2 level-2 ready.
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The encryption cipher is AES-XTS of 256/512 bit key size.
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MKEY is a memory region object in the hardware,
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that holds address translation information and attributes per memory area.
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Its ID must be tied to addresses provided to the hardware.
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The encryption operations are performed with MKEY read/write transactions,
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when the MKEY is configured to perform crypto operations.
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The encryption does not require text to be aligned to the AES block size (128b).
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The PMD uses ``libibverbs`` and ``libmlx5`` to access the device firmware
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or to access the hardware components directly.
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There are different levels of objects and bypassing abilities.
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To get the best performances:
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- Verbs is a complete high-level generic API.
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- Direct Verbs is a device-specific API.
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- DevX allows to access firmware objects.
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Enabling ``librte_crypto_mlx5`` causes DPDK applications
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to be linked against libibverbs.
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Driver options
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--------------
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- ``class`` parameter [string]
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Select the class of the driver that should probe the device.
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`crypto` for the mlx5 crypto driver.
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Supported NICs
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--------------
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* Mellanox\ |reg| ConnectX\ |reg|-6 200G MCX654106A-HCAT (2x200G)
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Prerequisites
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-------------
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- Mellanox OFED version: **5.3**
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see :doc:`../../nics/mlx5` guide for more Mellanox OFED details.
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- Compilation can be done also with rdma-core v15+.
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see :doc:`../../nics/mlx5` guide for more rdma-core details.
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@ -216,6 +216,7 @@ enum mlx5_class {
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MLX5_CLASS_VDPA = RTE_BIT64(1),
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MLX5_CLASS_REGEX = RTE_BIT64(2),
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MLX5_CLASS_COMPRESS = RTE_BIT64(3),
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MLX5_CLASS_CRYPTO = RTE_BIT64(4),
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};
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#define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
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@ -31,6 +31,7 @@ static const struct {
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{ .name = "net", .driver_class = MLX5_CLASS_NET },
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{ .name = "regex", .driver_class = MLX5_CLASS_REGEX },
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{ .name = "compress", .driver_class = MLX5_CLASS_COMPRESS },
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{ .name = "crypto", .driver_class = MLX5_CLASS_CRYPTO },
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};
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static const unsigned int mlx5_class_combinations[] = {
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@ -38,13 +39,26 @@ static const unsigned int mlx5_class_combinations[] = {
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MLX5_CLASS_VDPA,
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MLX5_CLASS_REGEX,
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MLX5_CLASS_COMPRESS,
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MLX5_CLASS_CRYPTO,
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MLX5_CLASS_NET | MLX5_CLASS_REGEX,
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MLX5_CLASS_VDPA | MLX5_CLASS_REGEX,
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MLX5_CLASS_NET | MLX5_CLASS_COMPRESS,
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MLX5_CLASS_VDPA | MLX5_CLASS_COMPRESS,
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MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS,
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MLX5_CLASS_NET | MLX5_CLASS_CRYPTO,
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MLX5_CLASS_VDPA | MLX5_CLASS_CRYPTO,
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MLX5_CLASS_REGEX | MLX5_CLASS_CRYPTO,
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MLX5_CLASS_COMPRESS | MLX5_CLASS_CRYPTO,
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MLX5_CLASS_NET | MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS,
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MLX5_CLASS_VDPA | MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS,
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MLX5_CLASS_NET | MLX5_CLASS_REGEX | MLX5_CLASS_CRYPTO,
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MLX5_CLASS_VDPA | MLX5_CLASS_REGEX | MLX5_CLASS_CRYPTO,
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MLX5_CLASS_NET | MLX5_CLASS_COMPRESS | MLX5_CLASS_CRYPTO,
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MLX5_CLASS_VDPA | MLX5_CLASS_COMPRESS | MLX5_CLASS_CRYPTO,
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MLX5_CLASS_NET | MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS |
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MLX5_CLASS_CRYPTO,
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MLX5_CLASS_VDPA | MLX5_CLASS_REGEX | MLX5_CLASS_COMPRESS |
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MLX5_CLASS_CRYPTO,
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/* New class combination should be added here. */
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};
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@ -9,17 +9,18 @@
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* @file
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*
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* RTE Mellanox PCI Driver Interface
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* Mellanox ConnectX PCI device supports multiple class: net,vdpa,regex and
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* compress devices. This layer enables creating such multiple class of devices
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* on a single PCI device by allowing to bind multiple class specific device
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* driver to attach to mlx5_pci driver.
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* Mellanox ConnectX PCI device supports multiple class: net,vdpa,regex,compress
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* and crypto devices. This layer enables creating such multiple class of
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* devices on a single PCI device by allowing to bind multiple class specific
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* device driver to attach to mlx5_pci driver.
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*
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* ----------- ------------ ------------- ----------------
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* | mlx5 | | mlx5 | | mlx5 | | mlx5 |
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* | net pmd | | vdpa pmd | | regex pmd | | compress pmd |
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* ----------- ------------ ------------- ----------------
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* \ \ / /
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* \ \ / /
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* -------- -------- --------- ------------ ----------
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* | mlx5 | | mlx5 | | mlx5 | | mlx5 | | mlx5 |
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* | net | | vdpa | | regex | | compress | | crypto |
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* | pmd | | pmd | | pmd | | pmd | | pmd |
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* -------- -------- --------- ------------ ----------
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* \ \ | / /
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* \ \ | / /
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* \ \_--------------_/ /
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* \_______________| mlx5 |_______________/
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* | pci common |
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@ -16,6 +16,7 @@ drivers = [
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'dpaa_sec',
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'dpaa2_sec',
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'kasumi',
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'mlx5',
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'mvsam',
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'nitrox',
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'null',
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27
drivers/crypto/mlx5/meson.build
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27
drivers/crypto/mlx5/meson.build
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@ -0,0 +1,27 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2021 NVIDIA Corporation & Affiliates
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if not is_linux
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build = false
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reason = 'only supported on Linux'
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subdir_done()
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endif
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fmt_name = 'mlx5_crypto'
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deps += ['common_mlx5', 'eal', 'cryptodev']
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sources = files(
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'mlx5_crypto.c',
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)
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cflags_options = [
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'-std=c11',
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'-Wno-strict-prototypes',
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'-D_BSD_SOURCE',
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'-D_DEFAULT_SOURCE',
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'-D_XOPEN_SOURCE=600',
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]
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foreach option:cflags_options
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if cc.has_argument(option)
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cflags += option
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endif
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endforeach
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263
drivers/crypto/mlx5/mlx5_crypto.c
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263
drivers/crypto/mlx5/mlx5_crypto.c
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2021 NVIDIA Corporation & Affiliates
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*/
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#include <rte_malloc.h>
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#include <rte_errno.h>
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#include <rte_log.h>
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#include <rte_pci.h>
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#include <mlx5_glue.h>
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#include <mlx5_common.h>
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#include <mlx5_common_pci.h>
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#include <mlx5_devx_cmds.h>
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#include <mlx5_common_os.h>
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#include "mlx5_crypto_utils.h"
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#include "mlx5_crypto.h"
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#define MLX5_CRYPTO_DRIVER_NAME crypto_mlx5
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#define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5
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#define MLX5_CRYPTO_FEATURE_FLAGS \
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RTE_CRYPTODEV_FF_HW_ACCELERATED
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TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =
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TAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);
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static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
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int mlx5_crypto_logtype;
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uint8_t mlx5_crypto_driver_id;
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static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME);
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static const struct rte_driver mlx5_drv = {
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.name = mlx5_crypto_drv_name,
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.alias = mlx5_crypto_drv_name
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};
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static struct cryptodev_driver mlx5_cryptodev_driver;
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static struct rte_cryptodev_ops mlx5_crypto_ops = {
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.dev_configure = NULL,
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.dev_start = NULL,
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.dev_stop = NULL,
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.dev_close = NULL,
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.dev_infos_get = NULL,
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.stats_get = NULL,
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.stats_reset = NULL,
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.queue_pair_setup = NULL,
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.queue_pair_release = NULL,
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.sym_session_get_size = NULL,
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.sym_session_configure = NULL,
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.sym_session_clear = NULL,
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.sym_get_raw_dp_ctx_size = NULL,
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.sym_configure_raw_dp_ctx = NULL,
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};
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static void
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mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv)
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{
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if (priv->pd != NULL) {
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claim_zero(mlx5_glue->dealloc_pd(priv->pd));
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priv->pd = NULL;
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}
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if (priv->uar != NULL) {
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mlx5_glue->devx_free_uar(priv->uar);
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priv->uar = NULL;
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}
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}
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static int
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mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv)
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{
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#ifdef HAVE_IBV_FLOW_DV_SUPPORT
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struct mlx5dv_obj obj;
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struct mlx5dv_pd pd_info;
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int ret;
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priv->pd = mlx5_glue->alloc_pd(priv->ctx);
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if (priv->pd == NULL) {
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DRV_LOG(ERR, "Failed to allocate PD.");
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return errno ? -errno : -ENOMEM;
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}
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obj.pd.in = priv->pd;
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obj.pd.out = &pd_info;
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ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
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if (ret != 0) {
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DRV_LOG(ERR, "Fail to get PD object info.");
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mlx5_glue->dealloc_pd(priv->pd);
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priv->pd = NULL;
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return -errno;
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}
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priv->pdn = pd_info.pdn;
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return 0;
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#else
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(void)priv;
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DRV_LOG(ERR, "Cannot get pdn - no DV support.");
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return -ENOTSUP;
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#endif /* HAVE_IBV_FLOW_DV_SUPPORT */
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}
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static int
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mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv)
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{
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if (mlx5_crypto_pd_create(priv) != 0)
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return -1;
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priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
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if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
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NULL) {
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rte_errno = errno;
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claim_zero(mlx5_glue->dealloc_pd(priv->pd));
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DRV_LOG(ERR, "Failed to allocate UAR.");
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return -1;
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}
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return 0;
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}
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/**
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* DPDK callback to register a PCI device.
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*
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* This function spawns crypto device out of a given PCI device.
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*
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* @param[in] pci_drv
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* PCI driver structure (mlx5_crypto_driver).
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* @param[in] pci_dev
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* PCI device information.
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*
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* @return
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* 0 on success, 1 to skip this driver, a negative errno value otherwise
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* and rte_errno is set.
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*/
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static int
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mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,
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struct rte_pci_device *pci_dev)
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{
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struct ibv_device *ibv;
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struct rte_cryptodev *crypto_dev;
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struct ibv_context *ctx;
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struct mlx5_crypto_priv *priv;
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struct mlx5_hca_attr attr = { 0 };
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struct rte_cryptodev_pmd_init_params init_params = {
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.name = "",
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.private_data_size = sizeof(struct mlx5_crypto_priv),
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.socket_id = pci_dev->device.numa_node,
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.max_nb_queue_pairs =
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RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,
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};
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RTE_SET_USED(pci_drv);
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if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
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DRV_LOG(ERR, "Non-primary process type is not supported.");
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rte_errno = ENOTSUP;
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return -rte_errno;
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}
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ibv = mlx5_os_get_ibv_device(&pci_dev->addr);
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if (ibv == NULL) {
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DRV_LOG(ERR, "No matching IB device for PCI slot "
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PCI_PRI_FMT ".", pci_dev->addr.domain,
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pci_dev->addr.bus, pci_dev->addr.devid,
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pci_dev->addr.function);
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return -rte_errno;
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}
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DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name);
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ctx = mlx5_glue->dv_open_device(ibv);
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if (ctx == NULL) {
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DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name);
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rte_errno = ENODEV;
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return -rte_errno;
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}
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if (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 ||
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attr.crypto == 0 || attr.aes_xts == 0) {
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DRV_LOG(ERR, "Not enough capabilities to support crypto "
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"operations, maybe old FW/OFED version?");
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claim_zero(mlx5_glue->close_device(ctx));
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rte_errno = ENOTSUP;
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return -ENOTSUP;
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}
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crypto_dev = rte_cryptodev_pmd_create(ibv->name, &pci_dev->device,
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&init_params);
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if (crypto_dev == NULL) {
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DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name);
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claim_zero(mlx5_glue->close_device(ctx));
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return -ENODEV;
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}
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DRV_LOG(INFO,
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"Crypto device %s was created successfully.", ibv->name);
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crypto_dev->dev_ops = &mlx5_crypto_ops;
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crypto_dev->dequeue_burst = NULL;
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crypto_dev->enqueue_burst = NULL;
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crypto_dev->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;
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crypto_dev->driver_id = mlx5_crypto_driver_id;
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priv = crypto_dev->data->dev_private;
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priv->ctx = ctx;
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priv->pci_dev = pci_dev;
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priv->crypto_dev = crypto_dev;
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if (mlx5_crypto_hw_global_prepare(priv) != 0) {
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rte_cryptodev_pmd_destroy(priv->crypto_dev);
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claim_zero(mlx5_glue->close_device(priv->ctx));
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return -1;
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}
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pthread_mutex_lock(&priv_list_lock);
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TAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);
|
||||
pthread_mutex_unlock(&priv_list_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mlx5_crypto_pci_remove(struct rte_pci_device *pdev)
|
||||
{
|
||||
struct mlx5_crypto_priv *priv = NULL;
|
||||
|
||||
pthread_mutex_lock(&priv_list_lock);
|
||||
TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next)
|
||||
if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0)
|
||||
break;
|
||||
if (priv)
|
||||
TAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next);
|
||||
pthread_mutex_unlock(&priv_list_lock);
|
||||
if (priv) {
|
||||
mlx5_crypto_hw_global_release(priv);
|
||||
rte_cryptodev_pmd_destroy(priv->crypto_dev);
|
||||
claim_zero(mlx5_glue->close_device(priv->ctx));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct rte_pci_id mlx5_crypto_pci_id_map[] = {
|
||||
{
|
||||
RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
|
||||
PCI_DEVICE_ID_MELLANOX_CONNECTX6)
|
||||
},
|
||||
{
|
||||
.vendor_id = 0
|
||||
}
|
||||
};
|
||||
|
||||
static struct mlx5_pci_driver mlx5_crypto_driver = {
|
||||
.driver_class = MLX5_CLASS_CRYPTO,
|
||||
.pci_driver = {
|
||||
.driver = {
|
||||
.name = RTE_STR(MLX5_CRYPTO_DRIVER_NAME),
|
||||
},
|
||||
.id_table = mlx5_crypto_pci_id_map,
|
||||
.probe = mlx5_crypto_pci_probe,
|
||||
.remove = mlx5_crypto_pci_remove,
|
||||
.drv_flags = 0,
|
||||
},
|
||||
};
|
||||
|
||||
RTE_INIT(rte_mlx5_crypto_init)
|
||||
{
|
||||
mlx5_common_init();
|
||||
if (mlx5_glue != NULL)
|
||||
mlx5_pci_driver_register(&mlx5_crypto_driver);
|
||||
}
|
||||
|
||||
RTE_PMD_REGISTER_CRYPTO_DRIVER(mlx5_cryptodev_driver, mlx5_drv,
|
||||
mlx5_crypto_driver_id);
|
||||
|
||||
RTE_LOG_REGISTER_DEFAULT(mlx5_crypto_logtype, NOTICE)
|
||||
RTE_PMD_EXPORT_NAME(MLX5_CRYPTO_DRIVER_NAME, __COUNTER__);
|
||||
RTE_PMD_REGISTER_PCI_TABLE(MLX5_CRYPTO_DRIVER_NAME, mlx5_crypto_pci_id_map);
|
||||
RTE_PMD_REGISTER_KMOD_DEP(MLX5_CRYPTO_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");
|
25
drivers/crypto/mlx5/mlx5_crypto.h
Normal file
25
drivers/crypto/mlx5/mlx5_crypto.h
Normal file
@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause
|
||||
* Copyright (c) 2021 NVIDIA Corporation & Affiliates
|
||||
*/
|
||||
|
||||
#ifndef MLX5_CRYPTO_H_
|
||||
#define MLX5_CRYPTO_H_
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <rte_cryptodev.h>
|
||||
#include <rte_cryptodev_pmd.h>
|
||||
|
||||
#include <mlx5_common_utils.h>
|
||||
|
||||
struct mlx5_crypto_priv {
|
||||
TAILQ_ENTRY(mlx5_crypto_priv) next;
|
||||
struct ibv_context *ctx; /* Device context. */
|
||||
struct rte_pci_device *pci_dev;
|
||||
struct rte_cryptodev *crypto_dev;
|
||||
void *uar; /* User Access Region. */
|
||||
uint32_t pdn; /* Protection Domain number. */
|
||||
struct ibv_pd *pd;
|
||||
};
|
||||
|
||||
#endif /* MLX5_CRYPTO_H_ */
|
19
drivers/crypto/mlx5/mlx5_crypto_utils.h
Normal file
19
drivers/crypto/mlx5/mlx5_crypto_utils.h
Normal file
@ -0,0 +1,19 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause
|
||||
* Copyright (c) 2021 NVIDIA Corporation & Affiliates
|
||||
*/
|
||||
|
||||
#ifndef RTE_PMD_MLX5_CRYPTO_UTILS_H_
|
||||
#define RTE_PMD_MLX5_CRYPTO_UTILS_H_
|
||||
|
||||
#include <mlx5_common.h>
|
||||
|
||||
extern int mlx5_crypto_logtype;
|
||||
|
||||
#define MLX5_CRYPTO_LOG_PREFIX "mlx5_crypto"
|
||||
/* Generic printf()-like logging macro with automatic line feed. */
|
||||
#define DRV_LOG(level, ...) \
|
||||
PMD_DRV_LOG_(level, mlx5_crypto_logtype, MLX5_CRYPTO_LOG_PREFIX, \
|
||||
__VA_ARGS__ PMD_DRV_LOG_STRIP PMD_DRV_LOG_OPAREN, \
|
||||
PMD_DRV_LOG_CPAREN)
|
||||
|
||||
#endif /* RTE_PMD_MLX5_CRYPTO_UTILS_H_ */
|
3
drivers/crypto/mlx5/version.map
Normal file
3
drivers/crypto/mlx5/version.map
Normal file
@ -0,0 +1,3 @@
|
||||
DPDK_21 {
|
||||
local: *;
|
||||
};
|
Loading…
Reference in New Issue
Block a user