compress/octeontx: support OCTEON TX2 SoC family

The octeontx2 9xxx SoC family support is added.

Signed-off-by: Mahipal Challa <mchalla@marvell.com>
Acked-by: Ashish Gupta <ashishg@marvell.com>
This commit is contained in:
Mahipal Challa 2022-02-28 09:10:35 +05:30 committed by Akhil Goyal
parent e689abaf8b
commit a80ea5c082
4 changed files with 24 additions and 1 deletions

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@ -63,6 +63,18 @@ typedef union {
uint64_t reserved_49_63 : 15;
#endif /* Word 0 - End */
} s;
struct zip_vqx_sbuf_addr_s9x {
#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
uint64_t reserved_53_63 : 11;
uint64_t ptr : 46;
uint64_t off : 7;
#else /* Word 0 - Little Endian */
uint64_t off : 7;
uint64_t ptr : 46;
uint64_t reserved_53_63 : 11;
#endif /* Word 0 - End */
} s9x;
} zip_vqx_sbuf_addr_t;
/**

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@ -58,7 +58,11 @@ zipvf_q_init(struct zipvf_qp *qp)
cmdq->iova = iova;
que_sbuf_addr.u = 0ull;
que_sbuf_addr.s.ptr = (cmdq->iova >> 7);
if (vf->pdev->id.device_id == PCI_DEVICE_ID_OCTEONTX2_ZIPVF)
que_sbuf_addr.s9x.ptr = (cmdq->iova >> 7);
else
que_sbuf_addr.s.ptr = (cmdq->iova >> 7);
zip_reg_write64(vf->vbar0, ZIP_VQ_SBUF_ADDR, que_sbuf_addr.u);
zip_q_enable(qp);

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@ -30,6 +30,7 @@ extern int octtx_zip_logtype_driver;
#define PCI_VENDOR_ID_CAVIUM 0x177D
/**< PCI device id of ZIP VF */
#define PCI_DEVICE_ID_OCTEONTX_ZIPVF 0xA037
#define PCI_DEVICE_ID_OCTEONTX2_ZIPVF 0xA083
/* maximum number of zip vf devices */
#define ZIP_MAX_VFS 8

View File

@ -85,7 +85,9 @@ zip_process_op(struct rte_comp_op *op,
op->status = RTE_COMP_OP_STATUS_ERROR;
}
#ifdef ZIP_DBG
ZIP_PMD_INFO("written %d\n", zresult->s.totalbyteswritten);
#endif
/* Update op stats */
switch (op->status) {
@ -630,6 +632,10 @@ static struct rte_pci_id pci_id_octtx_zipvf_table[] = {
RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
PCI_DEVICE_ID_OCTEONTX_ZIPVF),
},
{
RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
PCI_DEVICE_ID_OCTEONTX2_ZIPVF),
},
{
.device_id = 0
},