compress/octeontx: support OCTEON TX2 SoC family
The octeontx2 9xxx SoC family support is added. Signed-off-by: Mahipal Challa <mchalla@marvell.com> Acked-by: Ashish Gupta <ashishg@marvell.com>
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@ -63,6 +63,18 @@ typedef union {
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uint64_t reserved_49_63 : 15;
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#endif /* Word 0 - End */
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} s;
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struct zip_vqx_sbuf_addr_s9x {
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#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
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uint64_t reserved_53_63 : 11;
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uint64_t ptr : 46;
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uint64_t off : 7;
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#else /* Word 0 - Little Endian */
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uint64_t off : 7;
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uint64_t ptr : 46;
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uint64_t reserved_53_63 : 11;
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#endif /* Word 0 - End */
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} s9x;
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} zip_vqx_sbuf_addr_t;
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/**
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@ -58,7 +58,11 @@ zipvf_q_init(struct zipvf_qp *qp)
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cmdq->iova = iova;
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que_sbuf_addr.u = 0ull;
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que_sbuf_addr.s.ptr = (cmdq->iova >> 7);
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if (vf->pdev->id.device_id == PCI_DEVICE_ID_OCTEONTX2_ZIPVF)
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que_sbuf_addr.s9x.ptr = (cmdq->iova >> 7);
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else
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que_sbuf_addr.s.ptr = (cmdq->iova >> 7);
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zip_reg_write64(vf->vbar0, ZIP_VQ_SBUF_ADDR, que_sbuf_addr.u);
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zip_q_enable(qp);
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@ -30,6 +30,7 @@ extern int octtx_zip_logtype_driver;
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#define PCI_VENDOR_ID_CAVIUM 0x177D
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/**< PCI device id of ZIP VF */
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#define PCI_DEVICE_ID_OCTEONTX_ZIPVF 0xA037
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#define PCI_DEVICE_ID_OCTEONTX2_ZIPVF 0xA083
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/* maximum number of zip vf devices */
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#define ZIP_MAX_VFS 8
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@ -85,7 +85,9 @@ zip_process_op(struct rte_comp_op *op,
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op->status = RTE_COMP_OP_STATUS_ERROR;
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}
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#ifdef ZIP_DBG
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ZIP_PMD_INFO("written %d\n", zresult->s.totalbyteswritten);
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#endif
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/* Update op stats */
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switch (op->status) {
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@ -630,6 +632,10 @@ static struct rte_pci_id pci_id_octtx_zipvf_table[] = {
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RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
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PCI_DEVICE_ID_OCTEONTX_ZIPVF),
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},
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{
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RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
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PCI_DEVICE_ID_OCTEONTX2_ZIPVF),
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},
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{
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.device_id = 0
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},
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