raw/ifpga: add HE-LPBK AFU driver
HE-LPBK and HE-MEM-LPBK are host exerciser modules in OFS FPGA, HE-LPBK is used to test PCI bus and HE-MEM-LPBK is used to test local memory. This driver initialize the modules and report test result. Signed-off-by: Wei Huang <wei.huang@intel.com> Acked-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Rosen Xu <rosen.xu@intel.com>
This commit is contained in:
Wei Huang
Thomas Monjalon
parent
7d63899a5c
commit
a84edb506f
436
drivers/raw/ifpga/afu_pmd_he_lpbk.c
Normal file
436
drivers/raw/ifpga/afu_pmd_he_lpbk.c
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@ -0,0 +1,436 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 Intel Corporation
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*/
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#include <errno.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <poll.h>
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#include <sys/eventfd.h>
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#include <sys/ioctl.h>
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#include <rte_eal.h>
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#include <rte_malloc.h>
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#include <rte_memcpy.h>
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#include <rte_io.h>
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#include <rte_vfio.h>
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#include <rte_bus_pci.h>
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#include <rte_bus_ifpga.h>
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#include <rte_rawdev.h>
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#include "afu_pmd_core.h"
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#include "afu_pmd_he_lpbk.h"
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static int he_lpbk_afu_config(struct afu_rawdev *dev)
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{
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struct he_lpbk_priv *priv = NULL;
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struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
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struct he_lpbk_csr_cfg v;
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if (!dev)
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return -EINVAL;
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priv = (struct he_lpbk_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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cfg = &priv->he_lpbk_cfg;
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v.csr = 0;
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if (cfg->cont)
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v.cont = 1;
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v.mode = cfg->mode;
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v.trput_interleave = cfg->trput_interleave;
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if (cfg->multi_cl == 4)
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v.multicl_len = 2;
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else
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v.multicl_len = cfg->multi_cl - 1;
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IFPGA_RAWDEV_PMD_DEBUG("cfg: 0x%08x", v.csr);
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rte_write32(v.csr, priv->he_lpbk_ctx.addr + CSR_CFG);
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return 0;
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}
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static void he_lpbk_report(struct afu_rawdev *dev, uint32_t cl)
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{
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struct he_lpbk_priv *priv = NULL;
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struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
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struct he_lpbk_ctx *ctx = NULL;
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struct he_lpbk_dsm_status *stat = NULL;
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struct he_lpbk_status0 stat0;
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struct he_lpbk_status1 stat1;
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uint64_t swtest_msg = 0;
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uint64_t ticks = 0;
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uint64_t info = 0;
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double num, rd_bw, wr_bw;
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if (!dev || !dev->priv)
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return;
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priv = (struct he_lpbk_priv *)dev->priv;
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cfg = &priv->he_lpbk_cfg;
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ctx = &priv->he_lpbk_ctx;
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stat = ctx->status_ptr;
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swtest_msg = rte_read64(ctx->addr + CSR_SWTEST_MSG);
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stat0.csr = rte_read64(ctx->addr + CSR_STATUS0);
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stat1.csr = rte_read64(ctx->addr + CSR_STATUS1);
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if (cfg->cont)
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ticks = stat->num_clocks - stat->start_overhead;
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else
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ticks = stat->num_clocks -
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(stat->start_overhead + stat->end_overhead);
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if (cfg->freq_mhz == 0) {
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info = rte_read64(ctx->addr + CSR_HE_INFO0);
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IFPGA_RAWDEV_PMD_INFO("API version: %"PRIx64, info >> 16);
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cfg->freq_mhz = info & 0xffff;
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if (cfg->freq_mhz == 0) {
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IFPGA_RAWDEV_PMD_INFO("Frequency of AFU clock is unknown."
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" Assuming 350 MHz.");
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cfg->freq_mhz = 350;
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}
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}
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num = (double)stat0.num_reads;
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rd_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
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num = (double)stat0.num_writes;
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wr_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
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printf("Cachelines Read_Count Write_Count Pend_Read Pend_Write "
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"Clocks@%uMHz Rd_Bandwidth Wr_Bandwidth\n",
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cfg->freq_mhz);
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printf("%10u %10u %10u %10u %10u %12"PRIu64
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" %7.3f GB/s %7.3f GB/s\n",
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cl, stat0.num_reads, stat0.num_writes,
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stat1.num_pend_reads, stat1.num_pend_writes,
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ticks, rd_bw / 1e9, wr_bw / 1e9);
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printf("Test Message: 0x%"PRIx64"\n", swtest_msg);
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}
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static int he_lpbk_test(struct afu_rawdev *dev)
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{
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struct he_lpbk_priv *priv = NULL;
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struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
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struct he_lpbk_ctx *ctx = NULL;
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struct he_lpbk_csr_ctl ctl;
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uint32_t *ptr = NULL;
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uint32_t i, j, cl, val = 0;
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uint64_t sval = 0;
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int ret = 0;
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if (!dev)
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return -EINVAL;
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priv = (struct he_lpbk_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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cfg = &priv->he_lpbk_cfg;
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ctx = &priv->he_lpbk_ctx;
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ctl.csr = 0;
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rte_write32(ctl.csr, ctx->addr + CSR_CTL);
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rte_delay_us(1000);
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ctl.reset = 1;
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rte_write32(ctl.csr, ctx->addr + CSR_CTL);
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/* initialize DMA addresses */
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IFPGA_RAWDEV_PMD_DEBUG("src_addr: 0x%"PRIx64, ctx->src_iova);
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rte_write64(SIZE_TO_CLS(ctx->src_iova), ctx->addr + CSR_SRC_ADDR);
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IFPGA_RAWDEV_PMD_DEBUG("dst_addr: 0x%"PRIx64, ctx->dest_iova);
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rte_write64(SIZE_TO_CLS(ctx->dest_iova), ctx->addr + CSR_DST_ADDR);
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IFPGA_RAWDEV_PMD_DEBUG("dsm_addr: 0x%"PRIx64, ctx->dsm_iova);
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rte_write32(SIZE_TO_CLS(ctx->dsm_iova), ctx->addr + CSR_AFU_DSM_BASEL);
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rte_write32(SIZE_TO_CLS(ctx->dsm_iova) >> 32,
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ctx->addr + CSR_AFU_DSM_BASEH);
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ret = he_lpbk_afu_config(dev);
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if (ret)
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return ret;
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/* initialize src data */
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ptr = (uint32_t *)ctx->src_ptr;
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j = CLS_TO_SIZE(cfg->end) >> 2;
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for (i = 0; i < j; i++)
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*ptr++ = i;
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/* start test */
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for (cl = cfg->begin; cl <= cfg->end; cl += cfg->multi_cl) {
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memset(ctx->dest_ptr, 0, CLS_TO_SIZE(cl));
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memset(ctx->dsm_ptr, 0, DSM_SIZE);
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ctl.csr = 0;
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rte_write32(ctl.csr, ctx->addr + CSR_CTL);
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rte_delay_us(1000);
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ctl.reset = 1;
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rte_write32(ctl.csr, ctx->addr + CSR_CTL);
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rte_write32(cl - 1, ctx->addr + CSR_NUM_LINES);
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ctl.start = 1;
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rte_write32(ctl.csr, ctx->addr + CSR_CTL);
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if (cfg->cont) {
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rte_delay_ms(cfg->timeout * 1000);
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ctl.force_completion = 1;
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rte_write32(ctl.csr, ctx->addr + CSR_CTL);
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ret = dsm_poll_timeout(&ctx->status_ptr->test_complete,
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val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
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DSM_TIMEOUT);
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if (ret) {
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printf("DSM poll timeout\n");
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goto end;
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}
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} else {
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ret = dsm_poll_timeout(&ctx->status_ptr->test_complete,
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val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
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DSM_TIMEOUT);
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if (ret) {
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printf("DSM poll timeout\n");
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goto end;
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}
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ctl.force_completion = 1;
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rte_write32(ctl.csr, ctx->addr + CSR_CTL);
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}
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he_lpbk_report(dev, cl);
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i = 0;
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while (i++ < 100) {
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sval = rte_read64(ctx->addr + CSR_STATUS1);
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if (sval == 0)
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break;
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rte_delay_us(1000);
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}
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if (cfg->mode == NLB_MODE_LPBK) {
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ptr = (uint32_t *)ctx->dest_ptr;
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j = CLS_TO_SIZE(cl) >> 2;
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for (i = 0; i < j; i++) {
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if (*ptr++ != i) {
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IFPGA_RAWDEV_PMD_ERR("Data mismatch @ %u", i);
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break;
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}
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}
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}
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}
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end:
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return 0;
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}
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static int he_lpbk_ctx_release(struct afu_rawdev *dev)
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{
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struct he_lpbk_priv *priv = NULL;
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struct he_lpbk_ctx *ctx = NULL;
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if (!dev)
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return -EINVAL;
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priv = (struct he_lpbk_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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ctx = &priv->he_lpbk_ctx;
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rte_free(ctx->dsm_ptr);
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ctx->dsm_ptr = NULL;
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ctx->status_ptr = NULL;
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rte_free(ctx->src_ptr);
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ctx->src_ptr = NULL;
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rte_free(ctx->dest_ptr);
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ctx->dest_ptr = NULL;
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return 0;
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}
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static int he_lpbk_ctx_init(struct afu_rawdev *dev)
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{
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struct he_lpbk_priv *priv = NULL;
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struct he_lpbk_ctx *ctx = NULL;
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int ret = 0;
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if (!dev)
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return -EINVAL;
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priv = (struct he_lpbk_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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ctx = &priv->he_lpbk_ctx;
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ctx->addr = (uint8_t *)dev->addr;
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ctx->dsm_ptr = (uint8_t *)rte_zmalloc(NULL, DSM_SIZE, TEST_MEM_ALIGN);
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if (!ctx->dsm_ptr)
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return -ENOMEM;
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ctx->dsm_iova = rte_malloc_virt2iova(ctx->dsm_ptr);
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if (ctx->dsm_iova == RTE_BAD_IOVA) {
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ret = -ENOMEM;
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goto release_dsm;
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}
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ctx->src_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
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TEST_MEM_ALIGN);
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if (!ctx->src_ptr) {
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ret = -ENOMEM;
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goto release_dsm;
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}
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ctx->src_iova = rte_malloc_virt2iova(ctx->src_ptr);
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if (ctx->src_iova == RTE_BAD_IOVA) {
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ret = -ENOMEM;
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goto release_src;
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}
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ctx->dest_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
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TEST_MEM_ALIGN);
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if (!ctx->dest_ptr) {
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ret = -ENOMEM;
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goto release_src;
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}
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ctx->dest_iova = rte_malloc_virt2iova(ctx->dest_ptr);
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if (ctx->dest_iova == RTE_BAD_IOVA) {
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ret = -ENOMEM;
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goto release_dest;
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}
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ctx->status_ptr = (struct he_lpbk_dsm_status *)ctx->dsm_ptr;
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return 0;
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release_dest:
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rte_free(ctx->dest_ptr);
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ctx->dest_ptr = NULL;
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release_src:
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rte_free(ctx->src_ptr);
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ctx->src_ptr = NULL;
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release_dsm:
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rte_free(ctx->dsm_ptr);
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ctx->dsm_ptr = NULL;
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return ret;
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}
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static int he_lpbk_init(struct afu_rawdev *dev)
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{
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if (!dev)
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return -EINVAL;
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if (!dev->priv) {
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dev->priv = rte_zmalloc(NULL, sizeof(struct he_lpbk_priv), 0);
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if (!dev->priv)
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return -ENOMEM;
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}
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return he_lpbk_ctx_init(dev);
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}
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static int he_lpbk_config(struct afu_rawdev *dev, void *config,
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size_t config_size)
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{
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struct he_lpbk_priv *priv = NULL;
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struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
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if (!dev || !config || !config_size)
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return -EINVAL;
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priv = (struct he_lpbk_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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if (config_size != sizeof(struct rte_pmd_afu_he_lpbk_cfg))
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return -EINVAL;
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cfg = (struct rte_pmd_afu_he_lpbk_cfg *)config;
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if (cfg->mode > NLB_MODE_TRPUT)
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return -EINVAL;
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if ((cfg->multi_cl != 1) && (cfg->multi_cl != 2) &&
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(cfg->multi_cl != 4))
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return -EINVAL;
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if ((cfg->begin < MIN_CACHE_LINES) || (cfg->begin > MAX_CACHE_LINES))
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return -EINVAL;
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if ((cfg->end < cfg->begin) || (cfg->end > MAX_CACHE_LINES))
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return -EINVAL;
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rte_memcpy(&priv->he_lpbk_cfg, cfg, sizeof(priv->he_lpbk_cfg));
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return 0;
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}
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static int he_lpbk_close(struct afu_rawdev *dev)
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{
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if (!dev)
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return -EINVAL;
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he_lpbk_ctx_release(dev);
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rte_free(dev->priv);
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dev->priv = NULL;
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return 0;
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}
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static int he_lpbk_dump(struct afu_rawdev *dev, FILE *f)
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{
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struct he_lpbk_priv *priv = NULL;
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struct he_lpbk_ctx *ctx = NULL;
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if (!dev)
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return -EINVAL;
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priv = (struct he_lpbk_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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if (!f)
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f = stdout;
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ctx = &priv->he_lpbk_ctx;
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fprintf(f, "addr:\t\t%p\n", (void *)ctx->addr);
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fprintf(f, "dsm_ptr:\t%p\n", (void *)ctx->dsm_ptr);
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fprintf(f, "dsm_iova:\t0x%"PRIx64"\n", ctx->dsm_iova);
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fprintf(f, "src_ptr:\t%p\n", (void *)ctx->src_ptr);
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fprintf(f, "src_iova:\t0x%"PRIx64"\n", ctx->src_iova);
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fprintf(f, "dest_ptr:\t%p\n", (void *)ctx->dest_ptr);
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fprintf(f, "dest_iova:\t0x%"PRIx64"\n", ctx->dest_iova);
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fprintf(f, "status_ptr:\t%p\n", (void *)ctx->status_ptr);
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return 0;
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}
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static struct afu_ops he_lpbk_ops = {
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.init = he_lpbk_init,
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.config = he_lpbk_config,
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.start = NULL,
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.stop = NULL,
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.test = he_lpbk_test,
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.close = he_lpbk_close,
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.dump = he_lpbk_dump,
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.reset = NULL
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};
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struct afu_rawdev_drv he_lpbk_drv = {
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.uuid = { HE_LPBK_UUID_L, HE_LPBK_UUID_H },
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.ops = &he_lpbk_ops
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};
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AFU_PMD_REGISTER(he_lpbk_drv);
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struct afu_rawdev_drv he_mem_lpbk_drv = {
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.uuid = { HE_MEM_LPBK_UUID_L, HE_MEM_LPBK_UUID_H },
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.ops = &he_lpbk_ops
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};
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AFU_PMD_REGISTER(he_mem_lpbk_drv);
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126
drivers/raw/ifpga/afu_pmd_he_lpbk.h
Normal file
126
drivers/raw/ifpga/afu_pmd_he_lpbk.h
Normal file
@ -0,0 +1,126 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 Intel Corporation
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*/
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#ifndef AFU_PMD_HE_LPBK_H
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#define AFU_PMD_HE_LPBK_H
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||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "afu_pmd_core.h"
|
||||
#include "rte_pmd_afu.h"
|
||||
|
||||
#define HE_LPBK_UUID_L 0xb94b12284c31e02b
|
||||
#define HE_LPBK_UUID_H 0x56e203e9864f49a7
|
||||
#define HE_MEM_LPBK_UUID_L 0xbb652a578330a8eb
|
||||
#define HE_MEM_LPBK_UUID_H 0x8568ab4e6ba54616
|
||||
|
||||
/* HE-LBK & HE-MEM-LBK registers definition */
|
||||
#define CSR_SCRATCHPAD0 0x100
|
||||
#define CSR_SCRATCHPAD1 0x108
|
||||
#define CSR_AFU_DSM_BASEL 0x110
|
||||
#define CSR_AFU_DSM_BASEH 0x114
|
||||
#define CSR_SRC_ADDR 0x120
|
||||
#define CSR_DST_ADDR 0x128
|
||||
#define CSR_NUM_LINES 0x130
|
||||
#define CSR_CTL 0x138
|
||||
#define CSR_CFG 0x140
|
||||
#define CSR_INACT_THRESH 0x148
|
||||
#define CSR_INTERRUPT0 0x150
|
||||
#define CSR_SWTEST_MSG 0x158
|
||||
#define CSR_STATUS0 0x160
|
||||
#define CSR_STATUS1 0x168
|
||||
#define CSR_ERROR 0x170
|
||||
#define CSR_STRIDE 0x178
|
||||
#define CSR_HE_INFO0 0x180
|
||||
|
||||
#define DSM_SIZE 0x200000
|
||||
#define DSM_POLL_INTERVAL 5 /* ms */
|
||||
#define DSM_TIMEOUT 1000 /* ms */
|
||||
|
||||
#define NLB_BUF_SIZE 0x400000
|
||||
#define TEST_MEM_ALIGN 1024
|
||||
|
||||
struct he_lpbk_csr_ctl {
|
||||
union {
|
||||
uint32_t csr;
|
||||
struct {
|
||||
uint32_t reset:1;
|
||||
uint32_t start:1;
|
||||
uint32_t force_completion:1;
|
||||
uint32_t reserved:29;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct he_lpbk_csr_cfg {
|
||||
union {
|
||||
uint32_t csr;
|
||||
struct {
|
||||
uint32_t rsvd1:1;
|
||||
uint32_t cont:1;
|
||||
uint32_t mode:3;
|
||||
uint32_t multicl_len:2;
|
||||
uint32_t rsvd2:13;
|
||||
uint32_t trput_interleave:3;
|
||||
uint32_t test_cfg:5;
|
||||
uint32_t interrupt_on_error:1;
|
||||
uint32_t interrupt_testmode:1;
|
||||
uint32_t rsvd3:2;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct he_lpbk_status0 {
|
||||
union {
|
||||
uint64_t csr;
|
||||
struct {
|
||||
uint32_t num_writes;
|
||||
uint32_t num_reads;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct he_lpbk_status1 {
|
||||
union {
|
||||
uint64_t csr;
|
||||
struct {
|
||||
uint32_t num_pend_writes;
|
||||
uint32_t num_pend_reads;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct he_lpbk_dsm_status {
|
||||
uint32_t test_complete;
|
||||
uint32_t test_error;
|
||||
uint64_t num_clocks;
|
||||
uint32_t num_reads;
|
||||
uint32_t num_writes;
|
||||
uint32_t start_overhead;
|
||||
uint32_t end_overhead;
|
||||
};
|
||||
|
||||
struct he_lpbk_ctx {
|
||||
uint8_t *addr;
|
||||
uint8_t *dsm_ptr;
|
||||
uint64_t dsm_iova;
|
||||
uint8_t *src_ptr;
|
||||
uint64_t src_iova;
|
||||
uint8_t *dest_ptr;
|
||||
uint64_t dest_iova;
|
||||
struct he_lpbk_dsm_status *status_ptr;
|
||||
};
|
||||
|
||||
struct he_lpbk_priv {
|
||||
struct rte_pmd_afu_he_lpbk_cfg he_lpbk_cfg;
|
||||
struct he_lpbk_ctx he_lpbk_ctx;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* AFU_PMD_HE_LPBK_H */
|
||||
@ -14,7 +14,7 @@ deps += ['ethdev', 'rawdev', 'pci', 'bus_pci', 'kvargs',
|
||||
'bus_vdev', 'bus_ifpga', 'net', 'net_i40e', 'net_ipn3ke']
|
||||
|
||||
sources = files('ifpga_rawdev.c', 'rte_pmd_ifpga.c', 'afu_pmd_core.c',
|
||||
'afu_pmd_n3000.c')
|
||||
'afu_pmd_n3000.c', 'afu_pmd_he_lpbk.c')
|
||||
|
||||
includes += include_directories('base')
|
||||
includes += include_directories('../../net/ipn3ke')
|
||||
|
||||
@ -90,6 +90,20 @@ struct rte_pmd_afu_n3000_cfg {
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* HE-LPBK & HE-MEM-LPBK AFU configuration data structure.
|
||||
*/
|
||||
struct rte_pmd_afu_he_lpbk_cfg {
|
||||
uint32_t mode;
|
||||
uint32_t begin;
|
||||
uint32_t end;
|
||||
uint32_t multi_cl;
|
||||
uint32_t cont;
|
||||
uint32_t timeout;
|
||||
uint32_t trput_interleave;
|
||||
uint32_t freq_mhz;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user