net/sfc/base: add Medford2 head-of-line blocking stats
These stats are availble on Medford2 DPDK firmware variant which support equal stride super-buffer Rx mode. RXDP_HLB_IDLE capability bit is set when the stats are available. Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com> Reviewed-by: Andy Moreton <amoreton@solarflare.com>
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@ -544,8 +544,19 @@ ef10_mac_stats_get_mask(
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goto fail8;
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}
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if (encp->enc_hlb_counters) {
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const struct efx_mac_stats_range ef10_hlb[] = {
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{ EFX_MAC_RXDP_HLB_IDLE, EFX_MAC_RXDP_HLB_TIMEOUT },
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};
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if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
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ef10_hlb, EFX_ARRAY_SIZE(ef10_hlb))) != 0)
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goto fail9;
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}
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return (0);
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fail9:
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EFSYS_PROBE(fail9);
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fail8:
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EFSYS_PROBE(fail8);
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fail7:
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@ -999,6 +1010,13 @@ ef10_mac_stats_update(
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EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC]),
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&value);
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/* Head-of-line blocking */
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EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_IDLE, &value);
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EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_IDLE]), &value);
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EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_TIMEOUT, &value);
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EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_TIMEOUT]), &value);
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done:
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/* Read START generation counter */
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EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
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@ -1245,6 +1245,12 @@ ef10_get_datapath_caps(
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else
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encp->enc_fec_counters = B_FALSE;
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/* Check if the firmware provides head-of-line blocking counters */
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if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
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encp->enc_hlb_counters = B_TRUE;
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else
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encp->enc_hlb_counters = B_FALSE;
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if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
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/* Only one exclusive RSS context is available per port. */
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encp->enc_rx_scale_max_exclusive_contexts = 1;
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@ -1296,6 +1296,7 @@ typedef struct efx_nic_cfg_s {
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/* Firmware support for extended MAC_STATS buffer */
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uint32_t enc_mac_stats_nstats;
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boolean_t enc_fec_counters;
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boolean_t enc_hlb_counters;
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/* Firmware support for "FLAG" and "MARK" filter actions */
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boolean_t enc_filter_action_flag_supported;
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boolean_t enc_filter_action_mark_supported;
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