net/mlx5/hws: add context object
Context is the first mlx5dr object created, all sub objects table, matcher, rule, and action are created using the context. The context holds the capabilities and the send queues used for configuring the offloads to the HW. Signed-off-by: Alex Vesker <valex@nvidia.com>
This commit is contained in:
Alex Vesker
Raslan Darawsheh
parent
c55c2bf353
commit
b0290e56dd
223
drivers/net/mlx5/hws/mlx5dr_context.c
Normal file
223
drivers/net/mlx5/hws/mlx5dr_context.c
Normal file
@ -0,0 +1,223 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2022 NVIDIA Corporation & Affiliates
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*/
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#include "mlx5dr_internal.h"
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static int mlx5dr_context_pools_init(struct mlx5dr_context *ctx)
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{
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struct mlx5dr_pool_attr pool_attr = {0};
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uint8_t max_log_sz;
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int i;
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if (mlx5dr_pat_init_pattern_cache(&ctx->pattern_cache))
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return rte_errno;
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/* Create an STC pool per FT type */
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pool_attr.pool_type = MLX5DR_POOL_TYPE_STC;
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pool_attr.flags = MLX5DR_POOL_FLAGS_FOR_STC_POOL;
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max_log_sz = RTE_MIN(MLX5DR_POOL_STC_LOG_SZ, ctx->caps->stc_alloc_log_max);
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pool_attr.alloc_log_sz = RTE_MAX(max_log_sz, ctx->caps->stc_alloc_log_gran);
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for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {
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pool_attr.table_type = i;
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ctx->stc_pool[i] = mlx5dr_pool_create(ctx, &pool_attr);
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if (!ctx->stc_pool[i]) {
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DR_LOG(ERR, "Failed to allocate STC pool [%d]", i);
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goto free_stc_pools;
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}
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}
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return 0;
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free_stc_pools:
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for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++)
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if (ctx->stc_pool[i])
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mlx5dr_pool_destroy(ctx->stc_pool[i]);
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mlx5dr_pat_uninit_pattern_cache(ctx->pattern_cache);
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return rte_errno;
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}
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static void mlx5dr_context_pools_uninit(struct mlx5dr_context *ctx)
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{
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int i;
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mlx5dr_pat_uninit_pattern_cache(ctx->pattern_cache);
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for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {
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if (ctx->stc_pool[i])
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mlx5dr_pool_destroy(ctx->stc_pool[i]);
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}
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}
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static int mlx5dr_context_init_pd(struct mlx5dr_context *ctx,
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struct ibv_pd *pd)
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{
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struct mlx5dv_pd mlx5_pd = {0};
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struct mlx5dv_obj obj;
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int ret;
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if (pd) {
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ctx->pd = pd;
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} else {
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ctx->pd = mlx5_glue->alloc_pd(ctx->ibv_ctx);
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if (!ctx->pd) {
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DR_LOG(ERR, "Failed to allocate PD");
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rte_errno = errno;
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return rte_errno;
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}
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ctx->flags |= MLX5DR_CONTEXT_FLAG_PRIVATE_PD;
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}
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obj.pd.in = ctx->pd;
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obj.pd.out = &mlx5_pd;
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ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
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if (ret)
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goto free_private_pd;
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ctx->pd_num = mlx5_pd.pdn;
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return 0;
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free_private_pd:
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if (ctx->flags & MLX5DR_CONTEXT_FLAG_PRIVATE_PD)
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mlx5_glue->dealloc_pd(ctx->pd);
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return ret;
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}
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static int mlx5dr_context_uninit_pd(struct mlx5dr_context *ctx)
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{
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if (ctx->flags & MLX5DR_CONTEXT_FLAG_PRIVATE_PD)
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return mlx5_glue->dealloc_pd(ctx->pd);
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return 0;
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}
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static void mlx5dr_context_check_hws_supp(struct mlx5dr_context *ctx)
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{
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struct mlx5dr_cmd_query_caps *caps = ctx->caps;
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/* HWS not supported on device / FW */
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if (!caps->wqe_based_update) {
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DR_LOG(INFO, "Required HWS WQE based insertion cap not supported");
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return;
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}
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/* Current solution requires all rules to set reparse bit */
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if ((!caps->nic_ft.reparse || !caps->fdb_ft.reparse) ||
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!IS_BIT_SET(caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_ALWAYS)) {
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DR_LOG(INFO, "Required HWS reparse cap not supported");
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return;
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}
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/* FW/HW must support 8DW STE */
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if (!IS_BIT_SET(caps->ste_format, MLX5_IFC_RTC_STE_FORMAT_8DW)) {
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DR_LOG(INFO, "Required HWS STE format not supported");
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return;
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}
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/* Adding rules by hash and by offset are requirements */
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if (!IS_BIT_SET(caps->rtc_index_mode, MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH) ||
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!IS_BIT_SET(caps->rtc_index_mode, MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET)) {
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DR_LOG(INFO, "Required HWS RTC update mode not supported");
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return;
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}
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/* Support for SELECT definer ID is required */
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if (!IS_BIT_SET(caps->definer_format_sup, MLX5_IFC_DEFINER_FORMAT_ID_SELECT)) {
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DR_LOG(INFO, "Required HWS Dynamic definer not supported");
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return;
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}
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ctx->flags |= MLX5DR_CONTEXT_FLAG_HWS_SUPPORT;
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}
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static int mlx5dr_context_init_hws(struct mlx5dr_context *ctx,
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struct mlx5dr_context_attr *attr)
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{
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int ret;
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mlx5dr_context_check_hws_supp(ctx);
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if (!(ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT))
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return 0;
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ret = mlx5dr_context_init_pd(ctx, attr->pd);
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if (ret)
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return ret;
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ret = mlx5dr_context_pools_init(ctx);
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if (ret)
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goto uninit_pd;
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ret = mlx5dr_send_queues_open(ctx, attr->queues, attr->queue_size);
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if (ret)
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goto pools_uninit;
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return 0;
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pools_uninit:
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mlx5dr_context_pools_uninit(ctx);
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uninit_pd:
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mlx5dr_context_uninit_pd(ctx);
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return ret;
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}
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static void mlx5dr_context_uninit_hws(struct mlx5dr_context *ctx)
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{
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if (!(ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT))
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return;
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mlx5dr_send_queues_close(ctx);
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mlx5dr_context_pools_uninit(ctx);
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mlx5dr_context_uninit_pd(ctx);
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}
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struct mlx5dr_context *mlx5dr_context_open(struct ibv_context *ibv_ctx,
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struct mlx5dr_context_attr *attr)
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{
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struct mlx5dr_context *ctx;
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int ret;
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ctx = simple_calloc(1, sizeof(*ctx));
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if (!ctx) {
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rte_errno = ENOMEM;
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return NULL;
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}
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ctx->ibv_ctx = ibv_ctx;
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pthread_spin_init(&ctx->ctrl_lock, PTHREAD_PROCESS_PRIVATE);
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ctx->caps = simple_calloc(1, sizeof(*ctx->caps));
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if (!ctx->caps)
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goto free_ctx;
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ret = mlx5dr_cmd_query_caps(ibv_ctx, ctx->caps);
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if (ret)
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goto free_caps;
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ret = mlx5dr_context_init_hws(ctx, attr);
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if (ret)
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goto free_caps;
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return ctx;
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free_caps:
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simple_free(ctx->caps);
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free_ctx:
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simple_free(ctx);
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return NULL;
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}
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int mlx5dr_context_close(struct mlx5dr_context *ctx)
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{
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mlx5dr_context_uninit_hws(ctx);
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simple_free(ctx->caps);
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pthread_spin_destroy(&ctx->ctrl_lock);
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simple_free(ctx);
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return 0;
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}
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40
drivers/net/mlx5/hws/mlx5dr_context.h
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40
drivers/net/mlx5/hws/mlx5dr_context.h
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@ -0,0 +1,40 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2022 NVIDIA Corporation & Affiliates
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*/
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#ifndef MLX5DR_CONTEXT_H_
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#define MLX5DR_CONTEXT_H_
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enum mlx5dr_context_flags {
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MLX5DR_CONTEXT_FLAG_HWS_SUPPORT = 1 << 0,
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MLX5DR_CONTEXT_FLAG_PRIVATE_PD = 1 << 1,
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};
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enum mlx5dr_context_shared_stc_type {
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MLX5DR_CONTEXT_SHARED_STC_DECAP = 0,
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MLX5DR_CONTEXT_SHARED_STC_POP = 1,
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MLX5DR_CONTEXT_SHARED_STC_MAX = 2,
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};
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struct mlx5dr_context_common_res {
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struct mlx5dr_action_default_stc *default_stc;
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struct mlx5dr_action_shared_stc *shared_stc[MLX5DR_CONTEXT_SHARED_STC_MAX];
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struct mlx5dr_cmd_forward_tbl *default_miss;
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};
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struct mlx5dr_context {
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struct ibv_context *ibv_ctx;
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struct mlx5dr_cmd_query_caps *caps;
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struct ibv_pd *pd;
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uint32_t pd_num;
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struct mlx5dr_pool *stc_pool[MLX5DR_TABLE_TYPE_MAX];
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struct mlx5dr_context_common_res common_res[MLX5DR_TABLE_TYPE_MAX];
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struct mlx5dr_pattern_cache *pattern_cache;
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pthread_spinlock_t ctrl_lock;
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enum mlx5dr_context_flags flags;
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struct mlx5dr_send_engine *send_queue;
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size_t queues;
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LIST_HEAD(table_head, mlx5dr_table) head;
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};
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#endif /* MLX5DR_CONTEXT_H_ */
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