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net/ice/base: update Boot Configuration Section read of NVM

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Boot Configuration Section Block has been moved to the
Preserved Field Area (PFA) of NVM. So, this patch updates
the NVM reads that involve Boot Configuration Section.

Signed-off-by: Md Fahad Iqbal Polash <md.fahad.iqbal.polash@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
This commit is contained in:
Qi Zhang 2019-08-29 10:36:16 +08:00 committed by Ferruh Yigit
parent 07c417e5fc
commit b06499a433
4 changed files with 124 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/net/ice/base/ice_devids.h
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@ -13,5 +13,11 @@
#define ICE_DEV_ID_E810C_QSFP 0x1592
/* Intel(R) Ethernet Controller E810-C for SFP */
#define ICE_DEV_ID_E810C_SFP 0x1593
/* Intel(R) Ethernet Connection C822N for backplane */
#define ICE_DEV_ID_C822N_BACKPLANE 0x1890
/* Intel(R) Ethernet Connection C822N for QSFP */
#define ICE_DEV_ID_C822N_QSFP 0x1891
/* Intel(R) Ethernet Connection C822N for SFP */
#define ICE_DEV_ID_C822N_SFP 0x1892
#endif /* _ICE_DEVIDS_H_ */

39
drivers/net/ice/base/ice_nvm.c
View File

@ -263,9 +263,9 @@ enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
enum ice_status ice_init_nvm(struct ice_hw *hw)
{
struct ice_nvm_info *nvm = &hw->nvm;
u16 oem_hi, oem_lo, cfg_ptr;
u16 oem_hi, oem_lo, boot_cfg_tlv, boot_cfg_tlv_len;
u16 eetrack_lo, eetrack_hi;
enum ice_status status = ICE_SUCCESS;
enum ice_status status;
u32 fla, gens_stat;
u8 sr_size;
@ -284,12 +284,12 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
fla = rd32(hw, GLNVM_FLA);
if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
nvm->blank_nvm_mode = false;
} else { /* Blank programming mode */
} else {
/* Blank programming mode */
nvm->blank_nvm_mode = true;
status = ICE_ERR_NVM_BLANK_MODE;
ice_debug(hw, ICE_DBG_NVM,
"NVM init error: unsupported blank mode.\n");
return status;
return ICE_ERR_NVM_BLANK_MODE;
}
status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
@ -312,19 +312,37 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
/* the following devices do not have boot_cfg_tlv yet */
if (hw->device_id == ICE_DEV_ID_C822N_BACKPLANE ||
hw->device_id == ICE_DEV_ID_C822N_QSFP ||
hw->device_id == ICE_DEV_ID_C822N_SFP)
return status;
status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
ICE_SR_BOOT_CFG_PTR);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read BOOT_CONFIG_PTR.\n");
ice_debug(hw, ICE_DBG_INIT,
"Failed to read Boot Configuration Block TLV.\n");
return status;
}
status = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);
/* Boot Configuration Block must have length at least 2 words
* (Combo Image Version High and Combo Image Version Low)
*/
if (boot_cfg_tlv_len < 2) {
ice_debug(hw, ICE_DBG_INIT,
"Invalid Boot Configuration Block TLV size.\n");
return ICE_ERR_INVAL_SIZE;
}
status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF),
&oem_hi);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
return status;
}
status = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),
status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF + 1),
&oem_lo);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
@ -332,7 +350,8 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
}
nvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;
return status;
return ICE_SUCCESS;
}

87
drivers/net/ice/base/ice_nvm.h Normal file
View File

@ -0,0 +1,87 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2001-2019
*/
#ifndef _ICE_NVM_H_
#define _ICE_NVM_H_
#define ICE_NVM_CMD_READ 0x0000000B
#define ICE_NVM_CMD_WRITE 0x0000000C
/* NVM Access config bits */
#define ICE_NVM_CFG_MODULE_M MAKEMASK(0xFF, 0)
#define ICE_NVM_CFG_MODULE_S 0
#define ICE_NVM_CFG_FLAGS_M MAKEMASK(0xF, 8)
#define ICE_NVM_CFG_FLAGS_S 8
#define ICE_NVM_CFG_EXT_FLAGS_M MAKEMASK(0xF, 12)
#define ICE_NVM_CFG_EXT_FLAGS_S 12
#define ICE_NVM_CFG_ADAPTER_INFO_M MAKEMASK(0xFFFF, 16)
#define ICE_NVM_CFG_ADAPTER_INFO_S 16
/* NVM Read Get Driver Features */
#define ICE_NVM_GET_FEATURES_MODULE 0xE
#define ICE_NVM_GET_FEATURES_FLAGS 0xF
/* NVM Read/Write Mapped Space */
#define ICE_NVM_REG_RW_MODULE 0x0
#define ICE_NVM_REG_RW_FLAGS 0x1
#define ICE_NVM_ACCESS_MAJOR_VER 0
#define ICE_NVM_ACCESS_MINOR_VER 5
/* NVM Access feature flags. Other bits in the features field are reserved and
* should be set to zero when reporting the ice_nvm_features structure.
*/
#define ICE_NVM_FEATURES_0_REG_ACCESS BIT(1)
/* NVM Access Features */
struct ice_nvm_features {
u8 major; /* Major version (informational only) */
u8 minor; /* Minor version (informational only) */
u16 size; /* size of ice_nvm_features structure */
u8 features[12]; /* Array of feature bits */
};
/* NVM Access command */
struct ice_nvm_access_cmd {
u32 command; /* NVM command: READ or WRITE */
u32 config; /* NVM command configuration */
u32 offset; /* offset to read/write, in bytes */
u32 data_size; /* size of data field, in bytes */
};
/* NVM Access data */
union ice_nvm_access_data {
u32 regval; /* Storage for register value */
struct ice_nvm_features drv_features; /* NVM features */
};
/* NVM Access registers */
#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
#define GL_HICR 0x00082040
#define GL_HICR_EN 0x00082044
#define GLGEN_CSR_DEBUG_C 0x00075750
#define GLPCI_LBARCTRL 0x0009DE74
#define GLNVM_GENS 0x000B6100
#define GLNVM_FLA 0x000B6108
#define ICE_NVM_ACCESS_GL_HIDA_MAX 15
#define ICE_NVM_ACCESS_GL_HIBA_MAX 1023
u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);
u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);
u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);
enum ice_status
ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
union ice_nvm_access_data *data);
enum ice_status
ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
union ice_nvm_access_data *data);
enum ice_status
ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
union ice_nvm_access_data *data);
enum ice_status
ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
union ice_nvm_access_data *data);
#endif /* _ICE_NVM_H_ */

4
drivers/net/ice/base/ice_type.h
View File

@ -916,9 +916,9 @@ enum ice_sw_fwd_act_type {
#define ICE_SR_MNG_CFG_PTR 0x0E
#define ICE_SR_EMP_MODULE_PTR 0x0F
#define ICE_SR_PBA_BLOCK_PTR 0x16
#define ICE_SR_BOOT_CFG_PTR 0x17
#define ICE_SR_BOOT_CFG_PTR 0x132
#define ICE_SR_NVM_WOL_CFG 0x19
#define ICE_NVM_OEM_VER_OFF 0x83
#define ICE_NVM_OEM_VER_OFF 0x02
#define ICE_SR_NVM_DEV_STARTER_VER 0x18
#define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
#define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28