net/mlx5: fix VLAN inner type matching on DR/DV
The rte_flow_item_vlan has the inner_type, which is missing on DR/DV flow engine. By adding this support, the example testpmd commands could be: - matching all vlan traffic with id 2: testpmd> flow create 0 ingress pattern eth / vlan vid is 2 / end actions queue index 2 / end - matching all ipv4 traffic in vlan with id 2: testpmd> flow create 0 ingress pattern eth / vlan vid is 2 inner_type is 0x0800 / end actions queue index 2 / end Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items") Cc: stable@dpdk.org Signed-off-by: Xiaoyu Min <jackmin@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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@ -3469,10 +3469,6 @@ flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
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{
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const struct rte_flow_item_vlan *vlan_m = item->mask;
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const struct rte_flow_item_vlan *vlan_v = item->spec;
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const struct rte_flow_item_vlan nic_mask = {
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.tci = RTE_BE16(0x0fff),
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.inner_type = RTE_BE16(0xffff),
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};
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void *headers_m;
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void *headers_v;
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uint16_t tci_m;
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@ -3481,7 +3477,7 @@ flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
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if (!vlan_v)
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return;
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if (!vlan_m)
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vlan_m = &nic_mask;
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vlan_m = &rte_flow_item_vlan_mask;
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if (inner) {
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headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
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inner_headers);
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@ -3507,6 +3503,10 @@ flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
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MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
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MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
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MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
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MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
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rte_be_to_cpu_16(vlan_m->inner_type));
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MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
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rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
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}
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/**
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