net/dpaa: support Rx interrupt enable and disable
This patch adds support for dpaa eth driver interrupt enable and disable callback functions. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
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@ -664,6 +664,12 @@ qman_free_global_portal(struct qman_portal *portal)
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return -1;
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}
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void
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qman_portal_uninhibit_isr(struct qman_portal *portal)
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{
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qm_isr_uninhibit(&portal->p);
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}
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struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
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const struct qman_cgrs *cgrs)
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{
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@ -1053,6 +1059,20 @@ int qman_irqsource_add(u32 bits)
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dpaa_set_bits(bits, &p->irq_sources);
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qm_isr_enable_write(&p->p, p->irq_sources);
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return 0;
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}
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int qman_fq_portal_irqsource_add(struct qman_portal *p, u32 bits)
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{
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bits = bits & QM_PIRQ_VISIBLE;
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/* Clear any previously remaining interrupt conditions in
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* QCSP_ISR. This prevents raising a false interrupt when
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* interrupt conditions are enabled in QCSP_IER.
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*/
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qm_isr_status_clear(&p->p, bits);
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dpaa_set_bits(bits, &p->irq_sources);
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qm_isr_enable_write(&p->p, p->irq_sources);
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return 0;
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}
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@ -1083,6 +1103,31 @@ int qman_irqsource_remove(u32 bits)
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return 0;
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}
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int qman_fq_portal_irqsource_remove(struct qman_portal *p, u32 bits)
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{
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u32 ier;
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/* Our interrupt handler only processes+clears status register bits that
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* are in p->irq_sources. As we're trimming that mask, if one of them
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* were to assert in the status register just before we remove it from
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* the enable register, there would be an interrupt-storm when we
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* release the IRQ lock. So we wait for the enable register update to
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* take effect in h/w (by reading it back) and then clear all other bits
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* in the status register. Ie. we clear them from ISR once it's certain
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* IER won't allow them to reassert.
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*/
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bits &= QM_PIRQ_VISIBLE;
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dpaa_clear_bits(bits, &p->irq_sources);
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qm_isr_enable_write(&p->p, p->irq_sources);
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ier = qm_isr_enable_read(&p->p);
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/* Using "~ier" (rather than "bits" or "~p->irq_sources") creates a
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* data-dependency, ie. to protect against re-ordering.
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*/
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qm_isr_status_clear(&p->p, ~ier);
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return 0;
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}
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u16 qman_affine_channel(int cpu)
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{
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if (cpu < 0) {
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@ -121,6 +121,11 @@ void qman_thread_irq(void)
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out_be32(qpcfg.addr_virt[DPAA_PORTAL_CI] + 0x36C0, 0);
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}
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void qman_fq_portal_thread_irq(struct qman_portal *qp)
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{
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qman_portal_uninhibit_isr(qp);
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}
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struct qman_portal *fsl_qman_fq_portal_create(int *fd)
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{
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struct qman_portal *portal = NULL;
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@ -157,6 +157,8 @@ qman_init_portal(struct qman_portal *portal,
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struct qman_portal *qman_alloc_global_portal(struct qm_portal_config *q_pcfg);
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int qman_free_global_portal(struct qman_portal *portal);
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void qman_portal_uninhibit_isr(struct qman_portal *portal);
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struct qm_portal_config *qm_get_unused_portal(void);
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struct qm_portal_config *qm_get_unused_portal_idx(uint32_t idx);
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@ -67,6 +67,7 @@ int bman_thread_fd(void);
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*/
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void qman_thread_irq(void);
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void bman_thread_irq(void);
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void qman_fq_portal_thread_irq(struct qman_portal *qp);
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void qman_clear_irq(void);
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@ -127,5 +127,8 @@ DPDK_19.11 {
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global:
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fsl_qman_fq_portal_create;
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qman_fq_portal_irqsource_add;
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qman_fq_portal_irqsource_remove;
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qman_fq_portal_thread_irq;
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} DPDK_19.05;
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2017 NXP
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* Copyright 2017-2019 NXP
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*
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*/
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/* System headers */
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@ -1027,6 +1027,40 @@ dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
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return ret;
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}
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static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
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uint16_t queue_id)
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{
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struct dpaa_if *dpaa_intf = dev->data->dev_private;
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struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
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if (!rxq->is_static)
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return -EINVAL;
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return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
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}
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static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
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uint16_t queue_id)
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{
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struct dpaa_if *dpaa_intf = dev->data->dev_private;
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struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
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uint32_t temp;
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ssize_t temp1;
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if (!rxq->is_static)
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return -EINVAL;
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qman_fq_portal_irqsource_remove(rxq->qp, ~0);
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temp1 = read(rxq->q_fd, &temp, sizeof(temp));
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if (temp1 != sizeof(temp))
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DPAA_EVENTDEV_ERR("irq read error");
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qman_fq_portal_thread_irq(rxq->qp);
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return 0;
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}
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static struct eth_dev_ops dpaa_devops = {
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.dev_configure = dpaa_eth_dev_configure,
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.dev_start = dpaa_eth_dev_start,
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@ -1064,6 +1098,9 @@ static struct eth_dev_ops dpaa_devops = {
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.mac_addr_set = dpaa_dev_set_mac_addr,
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.fw_version_get = dpaa_fw_version_get,
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.rx_queue_intr_enable = dpaa_dev_queue_intr_enable,
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.rx_queue_intr_disable = dpaa_dev_queue_intr_disable,
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};
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static bool
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