net/ice/base: init IMEM table for parser
Parse DDP section ICE_SID_RXPARSER_IMEM into an array of struct ice_imem_item. The Instruction Memory (IMEM) section contains three VLIW instructions for the ALUs, a key extraction instruction for the Parse Graph CAM, and several other fields. Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Junfeng Guo <junfeng.guo@intel.com>
This commit is contained in:
Qi Zhang
parent
7fe2d98070
commit
b3e73a812f
244
drivers/net/ice/base/ice_imem.c
Normal file
244
drivers/net/ice/base/ice_imem.c
Normal file
@ -0,0 +1,244 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2021 Intel Corporation
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*/
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#include "ice_common.h"
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#include "ice_parser_util.h"
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#define ICE_IMEM_TABLE_SIZE 192
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static void _imem_bst_bm_dump(struct ice_hw *hw, struct ice_bst_main *bm)
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{
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ice_info(hw, "boost main:\n");
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ice_info(hw, "\tal0 = %d\n", bm->al0);
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ice_info(hw, "\tal1 = %d\n", bm->al1);
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ice_info(hw, "\tal2 = %d\n", bm->al2);
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ice_info(hw, "\tpg = %d\n", bm->pg);
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}
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static void _imem_bst_kb_dump(struct ice_hw *hw, struct ice_bst_keybuilder *kb)
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{
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ice_info(hw, "boost key builder:\n");
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ice_info(hw, "\tpriority = %d\n", kb->priority);
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ice_info(hw, "\ttsr_ctrl = %d\n", kb->tsr_ctrl);
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}
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static void _imem_np_kb_dump(struct ice_hw *hw, struct ice_np_keybuilder *kb)
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{
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ice_info(hw, "next proto key builder:\n");
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ice_info(hw, "\tops = %d\n", kb->ops);
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ice_info(hw, "\tstart_or_reg0 = %d\n", kb->start_or_reg0);
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ice_info(hw, "\tlen_or_reg1 = %d\n", kb->len_or_reg1);
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}
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static void _imem_pg_kb_dump(struct ice_hw *hw, struct ice_pg_keybuilder *kb)
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{
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ice_info(hw, "parse graph key builder:\n");
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ice_info(hw, "\tflag0_ena = %d\n", kb->flag0_ena);
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ice_info(hw, "\tflag1_ena = %d\n", kb->flag1_ena);
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ice_info(hw, "\tflag2_ena = %d\n", kb->flag2_ena);
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ice_info(hw, "\tflag3_ena = %d\n", kb->flag3_ena);
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ice_info(hw, "\tflag0_idx = %d\n", kb->flag0_idx);
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ice_info(hw, "\tflag1_idx = %d\n", kb->flag1_idx);
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ice_info(hw, "\tflag2_idx = %d\n", kb->flag2_idx);
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ice_info(hw, "\tflag3_idx = %d\n", kb->flag3_idx);
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ice_info(hw, "\talu_reg_idx = %d\n", kb->alu_reg_idx);
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}
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static void _imem_alu_dump(struct ice_hw *hw, struct ice_alu *alu, int index)
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{
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ice_info(hw, "alu%d:\n", index);
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ice_info(hw, "\topc = %d\n", alu->opc);
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ice_info(hw, "\tsrc_start = %d\n", alu->src_start);
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ice_info(hw, "\tsrc_len = %d\n", alu->src_len);
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ice_info(hw, "\tshift_xlate_select = %d\n", alu->shift_xlate_select);
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ice_info(hw, "\tshift_xlate_key = %d\n", alu->shift_xlate_key);
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ice_info(hw, "\tsrc_reg_id = %d\n", alu->src_reg_id);
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ice_info(hw, "\tdst_reg_id = %d\n", alu->dst_reg_id);
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ice_info(hw, "\tinc0 = %d\n", alu->inc0);
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ice_info(hw, "\tinc1 = %d\n", alu->inc1);
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ice_info(hw, "\tproto_offset_opc = %d\n", alu->proto_offset_opc);
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ice_info(hw, "\tproto_offset = %d\n", alu->proto_offset);
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ice_info(hw, "\tbranch_addr = %d\n", alu->branch_addr);
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ice_info(hw, "\timm = %d\n", alu->imm);
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ice_info(hw, "\tdst_start = %d\n", alu->dst_start);
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ice_info(hw, "\tdst_len = %d\n", alu->dst_len);
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ice_info(hw, "\tflags_extr_imm = %d\n", alu->flags_extr_imm);
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ice_info(hw, "\tflags_start_imm= %d\n", alu->flags_start_imm);
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}
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/**
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* ice_imem_dump - dump an imem item info
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* @ice_hw: pointer to the hardware structure
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* @item: imem item to dump
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*/
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void ice_imem_dump(struct ice_hw *hw, struct ice_imem_item *item)
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{
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ice_info(hw, "index = %d\n", item->idx);
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_imem_bst_bm_dump(hw, &item->b_m);
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_imem_bst_kb_dump(hw, &item->b_kb);
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ice_info(hw, "pg priority = %d\n", item->pg);
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_imem_np_kb_dump(hw, &item->np_kb);
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_imem_pg_kb_dump(hw, &item->pg_kb);
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_imem_alu_dump(hw, &item->alu0, 0);
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_imem_alu_dump(hw, &item->alu1, 1);
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_imem_alu_dump(hw, &item->alu2, 2);
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}
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/** The function parses a 4 bits Boost Main with below format:
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* BIT 0: ALU 0 (bm->alu0)
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* BIT 1: ALU 1 (bm->alu1)
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* BIT 2: ALU 2 (bm->alu2)
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* BIT 3: Parge Graph (bm->pg)
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*/
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static void _imem_bm_init(struct ice_bst_main *bm, u8 data)
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{
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bm->al0 = (data & 0x1) != 0;
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bm->al1 = (data & 0x2) != 0;
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bm->al2 = (data & 0x4) != 0;
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bm->pg = (data & 0x8) != 0;
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}
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/** The function parses a 10 bits Boost Main Build with below format:
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* BIT 0-7: Priority (bkb->priority)
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* BIT 8: TSR Control (bkb->tsr_ctrl)
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* BIT 9: Reserved
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*/
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static void _imem_bkb_init(struct ice_bst_keybuilder *bkb, u16 data)
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{
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bkb->priority = (u8)(data & 0xff);
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bkb->tsr_ctrl = (data & 0x100) != 0;
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}
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/** The function parses a 18 bits Next Protocol Key Build with below format:
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* BIT 0-1: Opcode kb->ops
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* BIT 2-9: Start / Reg 0 (kb->start_or_reg0)
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* BIT 10-17: Length / Reg 1 (kb->len_or_reg1)
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*/
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static void _imem_npkb_init(struct ice_np_keybuilder *kb, u32 data)
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{
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kb->ops = (u8)(data & 0x3);
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kb->start_or_reg0 = (u8)((data >> 2) & 0xff);
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kb->len_or_reg1 = (u8)((data >> 10) & 0xff);
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}
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/** The function parses a 35 bits Parse Graph Key Build with below format:
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* BIT 0: Flag 0 Enable (kb->flag0_ena)
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* BIT 1-6: Flag 0 Index (kb->flag0_idx)
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* BIT 7: Flag 1 Enable (kb->flag1_ena)
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* BIT 8-13: Flag 1 Index (kb->flag1_idx)
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* BIT 14: Flag 2 Enable (kb->flag2_ena)
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* BIT 15-20: Flag 2 Index (kb->flag2_idx)
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* BIT 21: Flag 3 Enable (kb->flag3_ena)
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* BIT 22-27: Flag 3 Index (kb->flag3_idx)
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* BIT 28-34: ALU Register Index (kb->alu_reg_idx)
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*/
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static void _imem_pgkb_init(struct ice_pg_keybuilder *kb, u64 data)
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{
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kb->flag0_ena = (data & 0x1) != 0;
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kb->flag0_idx = (u8)((data >> 1) & 0x3f);
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kb->flag1_ena = ((data >> 7) & 0x1) != 0;
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kb->flag1_idx = (u8)((data >> 8) & 0x3f);
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kb->flag2_ena = ((data >> 14) & 0x1) != 0;
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kb->flag2_idx = (u8)((data >> 15) & 0x3f);
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kb->flag3_ena = ((data >> 21) & 0x1) != 0;
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kb->flag3_idx = (u8)((data >> 22) & 0x3f);
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kb->alu_reg_idx = (u8)((data >> 28) & 0x7f);
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}
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/** The function parses a 96 bits ALU entry with below format:
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* BIT 0-5: Opcode (alu->opc)
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* BIT 6-13: Source Start (alu->src_start)
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* BIT 14-18: Source Length (alu->src_len)
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* BIT 19: Shift/Xlate Select (alu->shift_xlate_select)
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* BIT 20-23: Shift/Xlate Key (alu->shift_xlate_key)
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* BIT 24-30: Source Register ID (alu->src_reg_id)
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* BIT 31-37: Dest. Register ID (alu->dst_reg_id)
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* BIT 38: Inc0 (alu->inc0)
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* BIT 39: Inc1:(alu->inc1)
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* BIT 40:41 Protocol Offset Opcode (alu->proto_offset_opc)
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* BIT 42:49 Protocol Offset (alu->proto_offset)
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* BIT 50:57 Branch Address (alu->branch_addr)
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* BIT 58:73 Immediate (alu->imm)
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* BIT 74 Dedicated Flags Enable (alu->dedicate_flags_ena)
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* BIT 75:80 Dest. Start (alu->dst_start)
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* BIT 81:86 Dest. Length (alu->dst_len)
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* BIT 87 Flags Extract Imm. (alu->flags_extr_imm)
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* BIT 88:95 Flags Start/Immediate (alu->flags_start_imm)
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*
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* NOTE: the first 5 bits are skipped as the start bit is not
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* byte aligned.
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*/
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static void _imem_alu_init(struct ice_alu *alu, u8 *data)
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{
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u64 d64 = *(u64 *)data >> 5;
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alu->opc = (enum ice_alu_opcode)(d64 & 0x3f);
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alu->src_start = (u8)((d64 >> 6) & 0xff);
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alu->src_len = (u8)((d64 >> 14) & 0x1f);
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alu->shift_xlate_select = ((d64 >> 19) & 0x1) != 0;
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alu->shift_xlate_key = (u8)((d64 >> 20) & 0xf);
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alu->src_reg_id = (u8)((d64 >> 24) & 0x7f);
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alu->dst_reg_id = (u8)((d64 >> 31) & 0x7f);
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alu->inc0 = ((d64 >> 38) & 0x1) != 0;
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alu->inc1 = ((d64 >> 39) & 0x1) != 0;
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alu->proto_offset_opc = (u8)((d64 >> 40) & 0x3);
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alu->proto_offset = (u8)((d64 >> 42) & 0xff);
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alu->branch_addr = (u8)((d64 >> 50) & 0xff);
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d64 = *(u64 *)(&data[7]) >> 7;
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alu->imm = (u16)(d64 & 0xffff);
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alu->dedicate_flags_ena = ((d64 >> 16) & 0x1) != 0;
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alu->dst_start = (u8)((d64 >> 17) & 0x3f);
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alu->dst_len = (u8)((d64 >> 23) & 0x3f);
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alu->flags_extr_imm = ((d64 >> 29) & 0x1) != 0;
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alu->flags_start_imm = (u8)((d64 >> 30) & 0xff);
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}
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/** The function parses a 384 bits IMEM entry with below format:
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* BIT 0-3: Boost Main (ii->b_m)
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* BIT 4-13: Boost Key Build (ii->b_kb)
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* BIT 14-15: PG Priority (ii->pg)
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* BIT 16-33: Next Proto Key Build (ii->np_kb)
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* BIT 34-68: PG Key Build (ii->pg_kb)
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* BIT 69-164: ALU0 (ii->alu0)
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* BIT 165-260:ALU1 (ii->alu1)
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* BIT 261-356:ALU2 (ii->alu2)
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* BIT 357-383:Reserved
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*/
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static void _imem_parse_item(struct ice_hw *hw, u16 idx, void *item,
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void *data, int size)
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{
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struct ice_imem_item *ii = (struct ice_imem_item *)item;
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u8 *buf = (u8 *)data;
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ii->idx = idx;
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_imem_bm_init(&ii->b_m, buf[0]);
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_imem_bkb_init(&ii->b_kb, *((u16 *)(&buf[0])) >> 4);
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ii->pg = (u8)((buf[1] & 0xc0) >> 6);
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_imem_npkb_init(&ii->np_kb, *((u32 *)(&buf[2])));
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_imem_pgkb_init(&ii->pg_kb, *((u64 *)(&buf[2])) >> 18);
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_imem_alu_init(&ii->alu0, &buf[8]);
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_imem_alu_init(&ii->alu1, &buf[20]);
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_imem_alu_init(&ii->alu2, &buf[32]);
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if (hw->debug_mask & ICE_DBG_PARSER)
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ice_imem_dump(hw, ii);
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}
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/**
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* ice_imem_table_get - create an imem table
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* @ice_hw: pointer to the hardware structure
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*/
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struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw)
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{
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return (struct ice_imem_item *)
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ice_parser_create_table(hw, ICE_SID_RXPARSER_IMEM,
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sizeof(struct ice_imem_item),
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ICE_IMEM_TABLE_SIZE,
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ice_parser_sect_item_get,
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_imem_parse_item);
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}
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109
drivers/net/ice/base/ice_imem.h
Normal file
109
drivers/net/ice/base/ice_imem.h
Normal file
@ -0,0 +1,109 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2021 Intel Corporation
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*/
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#ifndef _ICE_IMEM_H_
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#define _ICE_IMEM_H_
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struct ice_bst_main {
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bool al0;
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bool al1;
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bool al2;
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bool pg;
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};
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struct ice_bst_keybuilder {
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u8 priority;
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bool tsr_ctrl;
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};
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struct ice_np_keybuilder {
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u8 ops;
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u8 start_or_reg0;
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u8 len_or_reg1;
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};
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struct ice_pg_keybuilder {
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bool flag0_ena;
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bool flag1_ena;
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bool flag2_ena;
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bool flag3_ena;
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u8 flag0_idx;
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u8 flag1_idx;
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u8 flag2_idx;
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u8 flag3_idx;
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u8 alu_reg_idx;
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};
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enum ice_alu_opcode {
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ICE_ALU_PARK = 0,
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ICE_ALU_MOV_ADD = 1,
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ICE_ALU_ADD = 2,
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ICE_ALU_MOV_AND = 4,
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ICE_ALU_AND = 5,
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ICE_ALU_AND_IMM = 6,
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ICE_ALU_MOV_OR = 7,
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ICE_ALU_OR = 8,
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ICE_ALU_MOV_XOR = 9,
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ICE_ALU_XOR = 10,
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ICE_ALU_NOP = 11,
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ICE_ALU_BR = 12,
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ICE_ALU_BREQ = 13,
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ICE_ALU_BRNEQ = 14,
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ICE_ALU_BRGT = 15,
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ICE_ALU_BRLT = 16,
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ICE_ALU_BRGEQ = 17,
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ICE_ALU_BRLEG = 18,
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ICE_ALU_SETEQ = 19,
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ICE_ALU_ANDEQ = 20,
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ICE_ALU_OREQ = 21,
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ICE_ALU_SETNEQ = 22,
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ICE_ALU_ANDNEQ = 23,
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ICE_ALU_ORNEQ = 24,
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ICE_ALU_SETGT = 25,
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ICE_ALU_ANDGT = 26,
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ICE_ALU_ORGT = 27,
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ICE_ALU_SETLT = 28,
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ICE_ALU_ANDLT = 29,
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ICE_ALU_ORLT = 30,
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ICE_ALU_MOV_SUB = 31,
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ICE_ALU_SUB = 32,
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ICE_ALU_INVALID = 64,
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};
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struct ice_alu {
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enum ice_alu_opcode opc;
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u8 src_start;
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u8 src_len;
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bool shift_xlate_select;
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u8 shift_xlate_key;
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u8 src_reg_id;
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u8 dst_reg_id;
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bool inc0;
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bool inc1;
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u8 proto_offset_opc;
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u8 proto_offset;
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u8 branch_addr;
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u16 imm;
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bool dedicate_flags_ena;
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u8 dst_start;
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u8 dst_len;
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bool flags_extr_imm;
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u8 flags_start_imm;
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};
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struct ice_imem_item {
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u16 idx;
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struct ice_bst_main b_m;
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struct ice_bst_keybuilder b_kb;
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u8 pg;
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struct ice_np_keybuilder np_kb;
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struct ice_pg_keybuilder pg_kb;
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struct ice_alu alu0;
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struct ice_alu alu1;
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struct ice_alu alu2;
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};
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void ice_imem_dump(struct ice_hw *hw, struct ice_imem_item *item);
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struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw);
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#endif /* _ICE_IMEM_H_ */
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@ -3,6 +3,94 @@
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*/
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#include "ice_common.h"
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#include "ice_parser_util.h"
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#define ICE_SEC_DATA_OFFSET 4
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#define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48
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/**
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* ice_parser_sect_item_get - parse a item from a section
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* @sect_type: section type
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* @section: section object
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* @index: index of the item to get
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* @offset: dummy as prototype of ice_pkg_enum_entry's last parameter
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*/
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void *ice_parser_sect_item_get(u32 sect_type, void *section,
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u32 index, u32 *offset)
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{
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struct ice_pkg_sect_hdr *hdr;
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int data_off = ICE_SEC_DATA_OFFSET;
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int size;
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if (!section)
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return NULL;
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switch (sect_type) {
|
||||
case ICE_SID_RXPARSER_IMEM:
|
||||
size = ICE_SID_RXPARSER_IMEM_ENTRY_SIZE;
|
||||
break;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
hdr = (struct ice_pkg_sect_hdr *)section;
|
||||
if (index >= LE16_TO_CPU(hdr->count))
|
||||
return NULL;
|
||||
|
||||
return (void *)((uintptr_t)section + data_off + index * size);
|
||||
}
|
||||
|
||||
/**
|
||||
* ice_parser_create_table - create a item table from a section
|
||||
* @hw: pointer to the hardware structure
|
||||
* @sect_type: section type
|
||||
* @item_size: item size in byte
|
||||
* @length: number of items in the table to create
|
||||
* @item_get: the function will be parsed to ice_pkg_enum_entry
|
||||
* @parser_item: the function to parse the item
|
||||
*/
|
||||
void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type,
|
||||
u32 item_size, u32 length,
|
||||
void *(*item_get)(u32 sect_type, void *section,
|
||||
u32 index, u32 *offset),
|
||||
void (*parse_item)(struct ice_hw *hw, u16 idx,
|
||||
void *item, void *data,
|
||||
int size))
|
||||
{
|
||||
struct ice_seg *seg = hw->seg;
|
||||
struct ice_pkg_enum state;
|
||||
u16 idx = 0;
|
||||
void *table;
|
||||
void *data;
|
||||
|
||||
if (!seg)
|
||||
return NULL;
|
||||
|
||||
table = ice_malloc(hw, item_size * length);
|
||||
if (!table) {
|
||||
ice_debug(hw, ICE_DBG_PARSER, "failed to allocate memory for table type %d.\n",
|
||||
sect_type);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM);
|
||||
do {
|
||||
data = ice_pkg_enum_entry(seg, &state, sect_type, NULL,
|
||||
item_get);
|
||||
seg = NULL;
|
||||
if (data) {
|
||||
struct ice_pkg_sect_hdr *hdr =
|
||||
(struct ice_pkg_sect_hdr *)state.sect;
|
||||
|
||||
idx = hdr->offset + state.entry_idx;
|
||||
parse_item(hw, idx,
|
||||
(void *)((uintptr_t)table + idx * item_size),
|
||||
data, item_size);
|
||||
}
|
||||
} while (data);
|
||||
|
||||
return table;
|
||||
}
|
||||
|
||||
/**
|
||||
* ice_parser_create - create a parser instance
|
||||
@ -11,6 +99,7 @@
|
||||
*/
|
||||
enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)
|
||||
{
|
||||
enum ice_status status;
|
||||
struct ice_parser *p;
|
||||
|
||||
p = (struct ice_parser *)ice_malloc(hw, sizeof(struct ice_parser));
|
||||
@ -20,8 +109,17 @@ enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)
|
||||
|
||||
p->hw = hw;
|
||||
|
||||
p->imem_table = ice_imem_table_get(hw);
|
||||
if (!p->imem_table) {
|
||||
status = ICE_ERR_PARAM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
*psr = p;
|
||||
return ICE_SUCCESS;
|
||||
err:
|
||||
ice_parser_destroy(p);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -30,5 +128,7 @@ enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)
|
||||
*/
|
||||
void ice_parser_destroy(struct ice_parser *psr)
|
||||
{
|
||||
ice_free(psr->hw, psr->imem_table);
|
||||
|
||||
ice_free(psr->hw, psr);
|
||||
}
|
||||
|
||||
@ -7,6 +7,9 @@
|
||||
|
||||
struct ice_parser {
|
||||
struct ice_hw *hw; /* pointer to the hardware structure */
|
||||
|
||||
/* load data from section ICE_SID_RX_PARSER_IMEM */
|
||||
struct ice_imem_item *imem_table;
|
||||
};
|
||||
|
||||
enum ice_status ice_parser_create(struct ice_hw *hw, struct ice_parser **psr);
|
||||
|
||||
25
drivers/net/ice/base/ice_parser_util.h
Normal file
25
drivers/net/ice/base/ice_parser_util.h
Normal file
@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause
|
||||
* Copyright(c) 2001-2021 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef _ICE_PARSER_UTIL_H_
|
||||
#define _ICE_PARSER_UTIL_H_
|
||||
|
||||
#include "ice_imem.h"
|
||||
|
||||
struct ice_pkg_sect_hdr {
|
||||
__le16 count;
|
||||
__le16 offset;
|
||||
};
|
||||
|
||||
void *ice_parser_sect_item_get(u32 sect_type, void *section,
|
||||
u32 index, u32 *offset);
|
||||
|
||||
void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type,
|
||||
u32 item_size, u32 length,
|
||||
void *(*handler)(u32 sect_type, void *section,
|
||||
u32 index, u32 *offset),
|
||||
void (*parse_item)(struct ice_hw *hw, u16 idx,
|
||||
void *item, void *data,
|
||||
int size));
|
||||
#endif /* _ICE_PARSER_UTIL_H_ */
|
||||
@ -141,6 +141,7 @@ static inline u32 ice_round_to_num(u32 N, u32 R)
|
||||
ICE_DBG_AQ_DESC | \
|
||||
ICE_DBG_AQ_DESC_BUF | \
|
||||
ICE_DBG_AQ_CMD)
|
||||
#define ICE_DBG_PARSER BIT_ULL(28)
|
||||
|
||||
#define ICE_DBG_USER BIT_ULL(31)
|
||||
#define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
|
||||
|
||||
@ -16,6 +16,7 @@ sources = [
|
||||
'ice_vlan_mode.c',
|
||||
'ice_ptp_hw.c',
|
||||
'ice_parser.c',
|
||||
'ice_imem.c',
|
||||
]
|
||||
|
||||
error_cflags = [
|
||||
|
||||
Loading…
Reference in New Issue
Block a user