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net/iavf: use write combining store for tail updates

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Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Gordon Noonan <gordon.noonan@intel.com>
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
This commit is contained in:
Gordon Noonan 2021-05-12 11:28:54 +01:00 committed by Qi Zhang
parent 920bdbf1bd
commit b5fcebb242
6 changed files with 14 additions and 9 deletions
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5
drivers/common/iavf/iavf_osdep.h
View File

@ -132,6 +132,11 @@ writeq(uint64_t value, volatile void *addr)
#define IAVF_PCI_REG_WRITE(reg, value) writel(value, reg)
#define IAVF_PCI_REG_WRITE_RELAXED(reg, value) writel_relaxed(value, reg)
#define IAVF_PCI_REG_WC_WRITE(reg, value) \
rte_write32_wc((rte_cpu_to_le_32(value)), reg)
#define IAVF_PCI_REG_WC_WRITE_RELAXED(reg, value) \
rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)
#define IAVF_READ_REG(hw, reg) rd32(hw, reg)
#define IAVF_WRITE_REG(hw, reg, value) wr32(hw, reg, value)

6
drivers/net/iavf/iavf_rxtx.c
View File

@ -1161,7 +1161,7 @@ iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
rxq->port_id, rxq->queue_id, rx_id, nb_hold);
rx_id = (uint16_t)((rx_id == 0) ?
(rxq->nb_rx_desc - 1) : (rx_id - 1));
IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
nb_hold = 0;
}
rxq->nb_rx_hold = nb_hold;
@ -1906,7 +1906,7 @@ iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
/* Update rx tail register */
rte_wmb();
IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
rxq->rx_free_trigger =
(uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
@ -2332,7 +2332,7 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
txq->port_id, txq->queue_id, tx_id, nb_tx);
IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
IAVF_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
txq->tx_tail = tx_id;
return nb_tx;

2
drivers/net/iavf/iavf_rxtx_vec_avx2.c
View File

@ -1500,7 +1500,7 @@ iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
txq->tx_tail = tx_id;
IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
return nb_pkts;
}

4
drivers/net/iavf/iavf_rxtx_vec_avx512.c
View File

@ -156,7 +156,7 @@ iavf_rxq_rearm(struct iavf_rx_queue *rxq)
(rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
/* Update the tail pointer on the NIC */
IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
}
#define IAVF_RX_LEN_MASK 0x80808080
@ -1958,7 +1958,7 @@ iavf_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
txq->tx_tail = tx_id;
IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
return nb_pkts;
}

2
drivers/net/iavf/iavf_rxtx_vec_common.h
View File

@ -570,7 +570,7 @@ iavf_rxq_rearm_common(struct iavf_rx_queue *rxq, __rte_unused bool avx512)
(rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
/* Update the tail pointer on the NIC */
IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
}
#endif

4
drivers/net/iavf/iavf_rxtx_vec_sse.c
View File

@ -88,7 +88,7 @@ iavf_rxq_rearm(struct iavf_rx_queue *rxq)
rx_id, rxq->rxrearm_start, rxq->rxrearm_nb);
/* Update the tail pointer on the NIC */
IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
}
static inline void
@ -1171,7 +1171,7 @@ iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_pkts=%u",
txq->port_id, txq->queue_id, tx_id, nb_pkts);
IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
return nb_pkts;
}