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i40e: use AQ for Rx control register read/write

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RX control register read/write functions are added, as directly
read/write may fail when under stress small traffic. After the
adminq is ready, all rx control registers should be read/written
by dedicated functions.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Acked-by: Remy Horton <remy.horton@intel.com>
This commit is contained in:
Helin Zhang 2016-03-08 16:14:31 +08:00 committed by Thomas Monjalon
parent 02558ae3a6
commit b6a0ec4182
9 changed files with 248 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
doc/guides/rel_notes/release_16_04.rst
View File

@ -224,6 +224,12 @@ Drivers
It generates a MAC address for each VFs during PF host initialization,
and keeps the VF MAC address the same among different VF launch.
* **i40e: Fixed failure of reading/writing Rx control registers.**
Fixed i40e issue of failing to read/write rx control registers when
under stress with traffic, which might result in application launch
failure.
* **aesni_mb: Fixed wrong return value when creating a device.**
cryptodev_aesni_mb_init() was returning the device id of the device created,

16
drivers/net/i40e/base/i40e_adminq_cmd.h
View File

@ -165,6 +165,8 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_set_port_parameters = 0x0203,
i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
i40e_aqc_opc_set_switch_config = 0x0205,
i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
i40e_aqc_opc_add_vsi = 0x0210,
i40e_aqc_opc_update_vsi_parameters = 0x0211,
@ -752,6 +754,20 @@ struct i40e_aqc_set_switch_config {
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
/* Read Receive control registers (direct 0x0206)
* Write Receive control registers (direct 0x0207)
* used for accessing Rx control registers that can be
* slow and need special handling when under high Rx load
*/
struct i40e_aqc_rx_ctl_reg_read_write {
__le32 reserved1;
__le32 address;
__le32 reserved2;
__le32 value;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
/* Add VSI (indirect 0x0210)
* this indirect command uses struct i40e_aqc_vsi_properties_data
* as the indirect buffer (128 bytes)

126
drivers/net/i40e/base/i40e_common.c
View File

@ -5356,7 +5356,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
return ret;
/* Read the PF Queue Filter control register */
val = rd32(hw, I40E_PFQF_CTL_0);
val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
/* Program required PE hash buckets for the PF */
val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
@ -5393,7 +5393,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
if (settings->enable_macvlan)
val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
wr32(hw, I40E_PFQF_CTL_0, val);
i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
return I40E_SUCCESS;
}
@ -6317,6 +6317,128 @@ enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
return status;
}
#endif /* PF_DRIVER */
/**
* i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
* @hw: pointer to the hw struct
* @reg_addr: register address
* @reg_val: ptr to register value
* @cmd_details: pointer to command details structure or NULL
*
* Use the firmware to read the Rx control register,
* especially useful if the Rx unit is under heavy pressure
**/
enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
u32 reg_addr, u32 *reg_val,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
enum i40e_status_code status;
if (reg_val == NULL)
return I40E_ERR_PARAM;
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
cmd_resp->address = CPU_TO_LE32(reg_addr);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
if (status == I40E_SUCCESS)
*reg_val = LE32_TO_CPU(cmd_resp->value);
return status;
}
/**
* i40e_read_rx_ctl - read from an Rx control register
* @hw: pointer to the hw struct
* @reg_addr: register address
**/
u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
{
enum i40e_status_code status = I40E_SUCCESS;
bool use_register;
int retry = 5;
u32 val = 0;
use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
if (!use_register) {
do_retry:
status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
i40e_msec_delay(1);
retry--;
goto do_retry;
}
}
/* if the AQ access failed, try the old-fashioned way */
if (status || use_register)
val = rd32(hw, reg_addr);
return val;
}
/**
* i40e_aq_rx_ctl_write_register
* @hw: pointer to the hw struct
* @reg_addr: register address
* @reg_val: register value
* @cmd_details: pointer to command details structure or NULL
*
* Use the firmware to write to an Rx control register,
* especially useful if the Rx unit is under heavy pressure
**/
enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
u32 reg_addr, u32 reg_val,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_rx_ctl_reg_read_write *cmd =
(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
enum i40e_status_code status;
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
cmd->address = CPU_TO_LE32(reg_addr);
cmd->value = CPU_TO_LE32(reg_val);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
return status;
}
/**
* i40e_write_rx_ctl - write to an Rx control register
* @hw: pointer to the hw struct
* @reg_addr: register address
* @reg_val: register value
**/
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
{
enum i40e_status_code status = I40E_SUCCESS;
bool use_register;
int retry = 5;
use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
if (!use_register) {
do_retry:
status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
reg_val, NULL);
if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
i40e_msec_delay(1);
retry--;
goto do_retry;
}
}
/* if the AQ access failed, try the old-fashioned way */
if (status || use_register)
wr32(hw, reg_addr, reg_val);
}
#ifdef VF_DRIVER
/**

36
drivers/net/i40e/base/i40e_osdep.h
View File

@ -117,6 +117,42 @@ do { \
##__VA_ARGS__); \
} while (0)
/* AQ commands based interfaces of i40e_read_rx_ctl() and i40e_write_rx_ctl()
* are required for reading/writing below registers, as reading/writing it
* directly may not function correctly if the device is under heavy small
* packet traffic. Note that those interfaces are available from FVL5 and not
* suitable before the AdminQ is ready during initialization.
*
* I40E_PFQF_CTL_0
* I40E_PFQF_HENA
* I40E_PFQF_FDALLOC
* I40E_PFQF_HREGION
* I40E_PFLAN_QALLOC
* I40E_VPQF_CTL
* I40E_VFQF_HENA
* I40E_VFQF_HREGION
* I40E_VSIQF_CTL
* I40E_VSILAN_QBASE
* I40E_VSILAN_QTABLE
* I40E_VSIQF_TCREGION
* I40E_PFQF_HKEY
* I40E_VFQF_HKEY
* I40E_PRTQF_CTL_0
* I40E_GLFCOE_RCTL
* I40E_GLFCOE_RSOF
* I40E_GLQF_CTL
* I40E_GLQF_SWAP
* I40E_GLQF_HASH_MSK
* I40E_GLQF_HASH_INSET
* I40E_GLQF_HSYM
* I40E_GLQF_FC_MSK
* I40E_GLQF_FC_INSET
* I40E_GLQF_FD_MSK
* I40E_PRTQF_FD_INSET
* I40E_PRTQF_FD_FLXINSET
* I40E_PRTQF_FD_MSK
*/
#define I40E_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
#define I40E_PCI_REG_ADDR(a, reg) \
((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))

8
drivers/net/i40e/base/i40e_prototype.h
View File

@ -516,6 +516,14 @@ enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
struct i40e_asq_cmd_details *cmd_details);
void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
u16 vsi_seid);
enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
u32 reg_addr, u32 *reg_val,
struct i40e_asq_cmd_details *cmd_details);
u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);
enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
u32 reg_addr, u32 reg_val,
struct i40e_asq_cmd_details *cmd_details);
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
#ifdef X722_SUPPORT
enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
struct i40e_aqc_arp_proxy_data *proxy_config,

66
drivers/net/i40e/i40e_ethdev.c
View File

@ -5788,11 +5788,11 @@ i40e_pf_disable_rss(struct i40e_pf *pf)
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
uint64_t hena;
hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
hena &= ~I40E_RSS_HENA_ALL;
I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
I40E_WRITE_FLUSH(hw);
}
@ -5825,7 +5825,7 @@ i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
uint16_t i;
for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
I40E_WRITE_FLUSH(hw);
}
@ -5854,7 +5854,7 @@ i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
uint16_t i;
for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
}
*key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
@ -5875,12 +5875,12 @@ i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
return ret;
rss_hf = rss_conf->rss_hf;
hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
hena &= ~I40E_RSS_HENA_ALL;
hena |= i40e_config_hena(rss_hf);
I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
I40E_WRITE_FLUSH(hw);
return 0;
@ -5895,8 +5895,8 @@ i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
uint64_t hena;
hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
if (rss_hf != 0) /* Enable RSS */
return -EINVAL;
@ -5920,8 +5920,8 @@ i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
&rss_conf->rss_key_len);
hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
rss_conf->rss_hf = i40e_parse_hena(hena);
return 0;
@ -6435,7 +6435,7 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf)
static void
i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
{
uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
*enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
}
@ -6444,7 +6444,7 @@ i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
static void
i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
{
uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
if (enable > 0) {
if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
@ -6461,7 +6461,7 @@ i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
}
reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
}
I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
I40E_WRITE_FLUSH(hw);
}
@ -6479,7 +6479,7 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw,
enum i40e_filter_pctype pctype;
memset(g_cfg, 0, sizeof(*g_cfg));
reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
if (reg & I40E_GLQF_CTL_HTOEP_MASK)
g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
else
@ -6494,7 +6494,7 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw,
/* Bit set indicats the coresponding flow type is supported */
g_cfg->valid_bit_mask[0] |= (1UL << i);
pctype = i40e_flowtype_to_pctype(i);
reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
}
@ -6567,10 +6567,10 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
pctype = i40e_flowtype_to_pctype(i);
reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
}
reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
/* Toeplitz */
if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
@ -6591,7 +6591,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
/* Use the default, and keep it as it is */
goto out;
I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
out:
I40E_WRITE_FLUSH(hw);
@ -7014,13 +7014,13 @@ i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
uint64_t reg = 0;
if (filter == RTE_ETH_FILTER_HASH) {
reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
reg <<= I40E_32_BIT_WIDTH;
reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
} else if (filter == RTE_ETH_FILTER_FDIR) {
reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
reg <<= I40E_32_BIT_WIDTH;
reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
}
return reg;
@ -7029,13 +7029,13 @@ i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
static void
i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
{
uint32_t reg = I40E_READ_REG(hw, addr);
uint32_t reg = i40e_read_rx_ctl(hw, addr);
PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
if (reg != val)
I40E_WRITE_REG(hw, addr, val);
i40e_write_rx_ctl(hw, addr, val);
PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
(uint32_t)I40E_READ_REG(hw, addr));
(uint32_t)i40e_read_rx_ctl(hw, addr));
}
static int
@ -7064,7 +7064,8 @@ i40e_set_hash_inset_mask(struct i40e_hw *hw,
uint8_t j, count = 0;
for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
reg = i40e_read_rx_ctl(hw,
I40E_GLQF_HASH_MSK(i, pctype));
if (reg & I40E_GLQF_HASH_MSK_FIELD)
count++;
}
@ -7105,7 +7106,8 @@ i40e_set_fd_inset_mask(struct i40e_hw *hw,
uint8_t j, count = 0;
for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
reg = i40e_read_rx_ctl(hw,
I40E_GLQF_FD_MSK(i, pctype));
if (reg & I40E_GLQF_FD_MSK_FIELD)
count++;
}
@ -7480,7 +7482,7 @@ i40e_hw_init(struct rte_eth_dev *dev)
i40e_enable_extended_tag(dev);
/* clear the PF Queue Filter control register */
I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
/* Disable symmetric hash per port */
i40e_set_symmetric_hash_enable_per_port(hw, 0);

28
drivers/net/i40e/i40e_ethdev_vf.c
View File

@ -2229,7 +2229,7 @@ i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
uint16_t i;
for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
I40E_WRITE_REG(hw, I40E_VFQF_HKEY(i), hash_key[i]);
i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
I40EVF_WRITE_FLUSH(hw);
}
@ -2258,7 +2258,7 @@ i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
uint16_t i;
for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
key_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HKEY(i));
key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
}
*key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
@ -2278,12 +2278,12 @@ i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
return ret;
rss_hf = rss_conf->rss_hf;
hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
hena &= ~I40E_RSS_HENA_ALL;
hena |= i40e_config_hena(rss_hf);
I40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
I40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
I40EVF_WRITE_FLUSH(hw);
return 0;
@ -2295,11 +2295,11 @@ i40evf_disable_rss(struct i40e_vf *vf)
struct i40e_hw *hw = I40E_VF_TO_HW(vf);
uint64_t hena;
hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
hena &= ~I40E_RSS_HENA_ALL;
I40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
I40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
I40EVF_WRITE_FLUSH(hw);
}
@ -2356,8 +2356,8 @@ i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
uint64_t hena;
hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
if (rss_hf != 0) /* Enable RSS */
return -EINVAL;
@ -2382,8 +2382,8 @@ i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
&rss_conf->rss_key_len);
hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
rss_conf->rss_hf = i40e_parse_hena(hena);
return 0;

13
drivers/net/i40e/i40e_fdir.c
View File

@ -52,6 +52,7 @@
#include "i40e_logs.h"
#include "base/i40e_type.h"
#include "base/i40e_prototype.h"
#include "i40e_ethdev.h"
#include "i40e_rxtx.h"
@ -369,11 +370,11 @@ i40e_init_flx_pld(struct i40e_pf *pf)
if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)pctype))
continue;
pf->fdir.flex_mask[pctype].word_mask = 0;
I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
}
}
}
@ -618,7 +619,7 @@ i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
flxinset = (flex_mask->word_mask <<
I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
I40E_PRTQF_FD_FLXINSET_INSET_MASK;
I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
for (i = 0; i < nb_bitmask; i++) {
fd_mask = (flex_mask->bitmask[i].mask <<
@ -628,7 +629,7 @@ i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
I40E_PRTQF_FD_MSK_OFFSET_MASK;
I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
}
}
@ -660,9 +661,9 @@ i40e_fdir_configure(struct rte_eth_dev *dev)
}
/* enable FDIR filter */
val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
i40e_init_flx_pld(pf); /* set flex config to default value */

6
drivers/net/i40e/i40e_pf.c
View File

@ -82,8 +82,8 @@ i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
* VF should use scatter range queues. So, it needn't
* to set QBASE in this register.
*/
I40E_WRITE_REG(hw, I40E_VSILAN_QBASE(vsi_id),
I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),
I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
/* Set to enable VFLAN_QTABLE[] registers valid */
I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
@ -108,7 +108,7 @@ i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
q2 = qbase + 2 * i + 1;
val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
I40E_WRITE_REG(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
}
I40E_WRITE_FLUSH(hw);