baseband/la12xx: support enqueue and dequeue
Add support for enqueue and dequeue the LDPC enc/dec from the modem device. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com> Acked-by: Akhil Goyal <gakhil@marvell.com> Acked-by: Nicolas Chautru <nicolas.chautru@intel.com>
This commit is contained in:
Hemant Agrawal
Akhil Goyal
parent
24d0ba2254
commit
b73d2f34b7
13
doc/guides/bbdevs/features/la12xx.ini
Normal file
13
doc/guides/bbdevs/features/la12xx.ini
Normal file
@ -0,0 +1,13 @@
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;
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; Supported features of the 'la12xx' bbdev driver.
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;
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; Refer to default.ini for the full list of available PMD features.
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;
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[Features]
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Turbo Decoder (4G) = N
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Turbo Encoder (4G) = N
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LDPC Decoder (5G) = Y
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LDPC Encoder (5G) = Y
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LLR/HARQ Compression = N
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HW Accelerated = Y
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BBDEV API = Y
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@ -78,3 +78,47 @@ For enabling logs, use the following EAL parameter:
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Using ``bb.la12xx`` as log matching criteria, all Baseband PMD logs can be
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enabled which are lower than logging ``level``.
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Test Application
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----------------
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BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
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the functionality of LA12xx for FEC encode and decode, depending on the device
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capabilities. The test application is located under app->test-bbdev folder and has the
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following options:
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.. code-block:: console
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"-p", "--testapp-path": specifies path to the bbdev test app.
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"-e", "--eal-params" : EAL arguments which are passed to the test app.
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"-t", "--timeout" : Timeout in seconds (default=300).
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"-c", "--test-cases" : Defines test cases to run. Run all if not specified.
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"-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
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"-n", "--num-ops" : Number of operations to process on device (default=32).
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"-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
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"-s", "--snr" : SNR in dB used when generating LLRs for bler tests.
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"-s", "--iter_max" : Number of iterations for LDPC decoder.
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"-l", "--num-lcores" : Number of lcores to run (default=16).
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"-i", "--init-device" : Initialise PF device with default values.
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To execute the test application tool using simple decode or encode data,
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type one of the following:
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.. code-block:: console
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./test-bbdev.py -e="--vdev=baseband_la12xx,socket_id=0,max_nb_queues=8" -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
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./test-bbdev.py -e="--vdev=baseband_la12xx,socket_id=0,max_nb_queues=8" -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
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The test application ``test-bbdev.py``, supports the ability to configure the PF device with
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a default set of values, if the "-i" or "- -init-device" option is included. The default values
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are defined in test_bbdev_perf.c.
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Test Vectors
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~~~~~~~~~~~~
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In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
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a range of additional tests under the test_vectors folder, which may be useful. The results
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of these tests will depend on the LA12xx FEC capabilities which may cause some
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testcases to be skipped, but no failure should be reported.
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@ -153,6 +153,11 @@ New Features
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Added support for more comprehensive CRC options.
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* **Added NXP LA12xx baseband PMD.**
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* Added a new baseband PMD driver for NXP LA12xx Software defined radio.
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* See the :doc:`../bbdevs/la12xx` for more details.
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* **Updated IPsec library.**
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* Added support for more AEAD algorithms AES_CCM, CHACHA20_POLY1305
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@ -120,6 +120,10 @@ la12xx_queue_release(struct rte_bbdev *dev, uint16_t q_id)
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((uint64_t) ((unsigned long) (A) \
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- ((uint64_t)ipc_priv->hugepg_start.host_vaddr)))
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#define MODEM_P2V(A) \
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((uint64_t) ((unsigned long) (A) \
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+ (unsigned long)(ipc_priv->peb_start.host_vaddr)))
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static int
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ipc_queue_configure(uint32_t channel_id,
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ipc_t instance,
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@ -336,6 +340,318 @@ static const struct rte_bbdev_ops pmd_ops = {
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.queue_release = la12xx_queue_release,
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.start = la12xx_start
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};
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static inline int
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is_bd_ring_full(uint32_t ci, uint32_t ci_flag,
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uint32_t pi, uint32_t pi_flag)
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{
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if (pi == ci) {
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if (pi_flag != ci_flag)
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return 1; /* Ring is Full */
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}
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return 0;
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}
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static inline int
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prepare_ldpc_enc_op(struct rte_bbdev_enc_op *bbdev_enc_op,
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struct bbdev_la12xx_q_priv *q_priv __rte_unused,
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struct rte_bbdev_op_data *in_op_data __rte_unused,
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struct rte_bbdev_op_data *out_op_data)
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{
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struct rte_bbdev_op_ldpc_enc *ldpc_enc = &bbdev_enc_op->ldpc_enc;
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uint32_t total_out_bits;
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total_out_bits = (ldpc_enc->tb_params.cab *
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ldpc_enc->tb_params.ea) + (ldpc_enc->tb_params.c -
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ldpc_enc->tb_params.cab) * ldpc_enc->tb_params.eb;
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ldpc_enc->output.length = (total_out_bits + 7)/8;
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rte_pktmbuf_append(out_op_data->data, ldpc_enc->output.length);
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return 0;
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}
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static inline int
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prepare_ldpc_dec_op(struct rte_bbdev_dec_op *bbdev_dec_op,
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struct bbdev_ipc_dequeue_op *bbdev_ipc_op,
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struct bbdev_la12xx_q_priv *q_priv __rte_unused,
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struct rte_bbdev_op_data *out_op_data __rte_unused)
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{
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struct rte_bbdev_op_ldpc_dec *ldpc_dec = &bbdev_dec_op->ldpc_dec;
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uint32_t total_out_bits;
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uint32_t num_code_blocks = 0;
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uint16_t sys_cols;
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sys_cols = (ldpc_dec->basegraph == 1) ? 22 : 10;
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if (ldpc_dec->tb_params.c == 1) {
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total_out_bits = ((sys_cols * ldpc_dec->z_c) -
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ldpc_dec->n_filler);
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/* 5G-NR protocol uses 16 bit CRC when output packet
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* size <= 3824 (bits). Otherwise 24 bit CRC is used.
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* Adjust the output bits accordingly
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*/
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if (total_out_bits - 16 <= 3824)
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total_out_bits -= 16;
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else
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total_out_bits -= 24;
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ldpc_dec->hard_output.length = (total_out_bits / 8);
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} else {
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total_out_bits = (((sys_cols * ldpc_dec->z_c) -
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ldpc_dec->n_filler - 24) *
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ldpc_dec->tb_params.c);
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ldpc_dec->hard_output.length = (total_out_bits / 8) - 3;
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}
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num_code_blocks = ldpc_dec->tb_params.c;
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bbdev_ipc_op->num_code_blocks = rte_cpu_to_be_32(num_code_blocks);
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return 0;
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}
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static int
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enqueue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *bbdev_op)
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{
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struct bbdev_la12xx_private *priv = q_priv->bbdev_priv;
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ipc_userspace_t *ipc_priv = priv->ipc_priv;
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ipc_instance_t *ipc_instance = ipc_priv->instance;
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struct bbdev_ipc_dequeue_op *bbdev_ipc_op;
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struct rte_bbdev_op_ldpc_enc *ldpc_enc;
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struct rte_bbdev_op_ldpc_dec *ldpc_dec;
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uint32_t q_id = q_priv->q_id;
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uint32_t ci, ci_flag, pi, pi_flag;
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ipc_ch_t *ch = &(ipc_instance->ch_list[q_id]);
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ipc_br_md_t *md = &(ch->md);
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size_t virt;
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char *huge_start_addr =
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(char *)q_priv->bbdev_priv->ipc_priv->hugepg_start.host_vaddr;
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struct rte_bbdev_op_data *in_op_data, *out_op_data;
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char *data_ptr;
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uint32_t l1_pcie_addr;
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int ret;
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ci = IPC_GET_CI_INDEX(q_priv->host_ci);
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ci_flag = IPC_GET_CI_FLAG(q_priv->host_ci);
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pi = IPC_GET_PI_INDEX(q_priv->host_pi);
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pi_flag = IPC_GET_PI_FLAG(q_priv->host_pi);
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rte_bbdev_dp_log(DEBUG, "before bd_ring_full: pi: %u, ci: %u,"
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"pi_flag: %u, ci_flag: %u, ring size: %u",
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pi, ci, pi_flag, ci_flag, q_priv->queue_size);
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if (is_bd_ring_full(ci, ci_flag, pi, pi_flag)) {
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rte_bbdev_dp_log(DEBUG, "bd ring full for queue id: %d", q_id);
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return IPC_CH_FULL;
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}
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virt = MODEM_P2V(q_priv->host_params->bd_m_modem_ptr[pi]);
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bbdev_ipc_op = (struct bbdev_ipc_dequeue_op *)virt;
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q_priv->bbdev_op[pi] = bbdev_op;
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switch (q_priv->op_type) {
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case RTE_BBDEV_OP_LDPC_ENC:
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ldpc_enc = &(((struct rte_bbdev_enc_op *)bbdev_op)->ldpc_enc);
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in_op_data = &ldpc_enc->input;
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out_op_data = &ldpc_enc->output;
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ret = prepare_ldpc_enc_op(bbdev_op, q_priv,
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in_op_data, out_op_data);
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if (ret) {
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rte_bbdev_log(ERR, "process_ldpc_enc_op fail, ret: %d",
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ret);
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return ret;
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}
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break;
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case RTE_BBDEV_OP_LDPC_DEC:
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ldpc_dec = &(((struct rte_bbdev_dec_op *)bbdev_op)->ldpc_dec);
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in_op_data = &ldpc_dec->input;
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out_op_data = &ldpc_dec->hard_output;
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ret = prepare_ldpc_dec_op(bbdev_op, bbdev_ipc_op,
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q_priv, out_op_data);
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if (ret) {
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rte_bbdev_log(ERR, "process_ldpc_dec_op fail, ret: %d",
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ret);
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return ret;
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}
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break;
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default:
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rte_bbdev_log(ERR, "unsupported bbdev_ipc op type");
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return -1;
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}
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if (in_op_data->data) {
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data_ptr = rte_pktmbuf_mtod(in_op_data->data, char *);
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l1_pcie_addr = (uint32_t)GUL_USER_HUGE_PAGE_ADDR +
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data_ptr - huge_start_addr;
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bbdev_ipc_op->in_addr = l1_pcie_addr;
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bbdev_ipc_op->in_len = in_op_data->length;
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}
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if (out_op_data->data) {
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data_ptr = rte_pktmbuf_mtod(out_op_data->data, char *);
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l1_pcie_addr = (uint32_t)GUL_USER_HUGE_PAGE_ADDR +
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data_ptr - huge_start_addr;
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bbdev_ipc_op->out_addr = rte_cpu_to_be_32(l1_pcie_addr);
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bbdev_ipc_op->out_len = rte_cpu_to_be_32(out_op_data->length);
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}
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/* Move Producer Index forward */
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pi++;
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/* Flip the PI flag, if wrapping */
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if (unlikely(q_priv->queue_size == pi)) {
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pi = 0;
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pi_flag = pi_flag ? 0 : 1;
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}
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if (pi_flag)
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IPC_SET_PI_FLAG(pi);
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else
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IPC_RESET_PI_FLAG(pi);
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q_priv->host_pi = pi;
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/* Wait for Data Copy & pi_flag update to complete before updating pi */
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rte_mb();
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/* now update pi */
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md->pi = rte_cpu_to_be_32(pi);
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rte_bbdev_dp_log(DEBUG, "enter: pi: %u, ci: %u,"
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"pi_flag: %u, ci_flag: %u, ring size: %u",
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pi, ci, pi_flag, ci_flag, q_priv->queue_size);
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return 0;
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}
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/* Enqueue decode burst */
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static uint16_t
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enqueue_dec_ops(struct rte_bbdev_queue_data *q_data,
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struct rte_bbdev_dec_op **ops, uint16_t nb_ops)
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{
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struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private;
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int nb_enqueued, ret;
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for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) {
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ret = enqueue_single_op(q_priv, ops[nb_enqueued]);
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if (ret)
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break;
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}
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q_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued;
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q_data->queue_stats.enqueued_count += nb_enqueued;
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return nb_enqueued;
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}
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/* Enqueue encode burst */
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static uint16_t
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enqueue_enc_ops(struct rte_bbdev_queue_data *q_data,
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struct rte_bbdev_enc_op **ops, uint16_t nb_ops)
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{
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struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private;
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int nb_enqueued, ret;
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for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) {
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ret = enqueue_single_op(q_priv, ops[nb_enqueued]);
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if (ret)
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break;
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}
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q_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued;
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q_data->queue_stats.enqueued_count += nb_enqueued;
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return nb_enqueued;
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}
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/* Dequeue encode burst */
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static void *
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dequeue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *dst)
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{
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void *op;
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uint32_t ci, ci_flag;
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uint32_t temp_ci;
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temp_ci = q_priv->host_params->ci;
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if (temp_ci == q_priv->host_ci)
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return NULL;
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ci = IPC_GET_CI_INDEX(q_priv->host_ci);
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ci_flag = IPC_GET_CI_FLAG(q_priv->host_ci);
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rte_bbdev_dp_log(DEBUG,
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"ci: %u, ci_flag: %u, ring size: %u",
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ci, ci_flag, q_priv->queue_size);
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op = q_priv->bbdev_op[ci];
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rte_memcpy(dst, q_priv->msg_ch_vaddr[ci],
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sizeof(struct bbdev_ipc_enqueue_op));
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/* Move Consumer Index forward */
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ci++;
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/* Flip the CI flag, if wrapping */
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if (q_priv->queue_size == ci) {
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ci = 0;
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ci_flag = ci_flag ? 0 : 1;
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}
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if (ci_flag)
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IPC_SET_CI_FLAG(ci);
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else
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IPC_RESET_CI_FLAG(ci);
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q_priv->host_ci = ci;
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rte_bbdev_dp_log(DEBUG,
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"exit: ci: %u, ci_flag: %u, ring size: %u",
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ci, ci_flag, q_priv->queue_size);
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return op;
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}
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/* Dequeue decode burst */
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static uint16_t
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dequeue_dec_ops(struct rte_bbdev_queue_data *q_data,
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struct rte_bbdev_dec_op **ops, uint16_t nb_ops)
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{
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struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private;
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struct bbdev_ipc_enqueue_op bbdev_ipc_op;
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int nb_dequeued;
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for (nb_dequeued = 0; nb_dequeued < nb_ops; nb_dequeued++) {
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ops[nb_dequeued] = dequeue_single_op(q_priv, &bbdev_ipc_op);
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if (!ops[nb_dequeued])
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break;
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ops[nb_dequeued]->status = bbdev_ipc_op.status;
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}
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q_data->queue_stats.dequeued_count += nb_dequeued;
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return nb_dequeued;
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}
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/* Dequeue encode burst */
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static uint16_t
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dequeue_enc_ops(struct rte_bbdev_queue_data *q_data,
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struct rte_bbdev_enc_op **ops, uint16_t nb_ops)
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{
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struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private;
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struct bbdev_ipc_enqueue_op bbdev_ipc_op;
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int nb_enqueued;
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for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) {
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ops[nb_enqueued] = dequeue_single_op(q_priv, &bbdev_ipc_op);
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if (!ops[nb_enqueued])
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break;
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ops[nb_enqueued]->status = bbdev_ipc_op.status;
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}
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q_data->queue_stats.enqueued_count += nb_enqueued;
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return nb_enqueued;
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}
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static struct hugepage_info *
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get_hugepage_info(void)
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{
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@ -718,6 +1034,10 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev,
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bbdev->dequeue_dec_ops = NULL;
|
||||
bbdev->enqueue_enc_ops = NULL;
|
||||
bbdev->enqueue_dec_ops = NULL;
|
||||
bbdev->dequeue_ldpc_enc_ops = dequeue_enc_ops;
|
||||
bbdev->dequeue_ldpc_dec_ops = dequeue_dec_ops;
|
||||
bbdev->enqueue_ldpc_enc_ops = enqueue_enc_ops;
|
||||
bbdev->enqueue_ldpc_dec_ops = enqueue_dec_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -73,6 +73,25 @@ typedef struct {
|
||||
_IOWR(GUL_IPC_MAGIC, 5, struct ipc_msg *)
|
||||
#define IOCTL_GUL_IPC_CHANNEL_RAISE_INTERRUPT _IOW(GUL_IPC_MAGIC, 6, int *)
|
||||
|
||||
#define GUL_USER_HUGE_PAGE_OFFSET (0)
|
||||
#define GUL_PCI1_ADDR_BASE (0x00000000ULL)
|
||||
|
||||
#define GUL_USER_HUGE_PAGE_ADDR (GUL_PCI1_ADDR_BASE + GUL_USER_HUGE_PAGE_OFFSET)
|
||||
|
||||
/* IPC PI/CI index & flag manipulation helpers */
|
||||
#define IPC_PI_CI_FLAG_MASK 0x80000000 /* (1<<31) */
|
||||
#define IPC_PI_CI_INDEX_MASK 0x7FFFFFFF /* ~(1<<31) */
|
||||
|
||||
#define IPC_SET_PI_FLAG(x) (x |= IPC_PI_CI_FLAG_MASK)
|
||||
#define IPC_RESET_PI_FLAG(x) (x &= IPC_PI_CI_INDEX_MASK)
|
||||
#define IPC_GET_PI_FLAG(x) (x >> 31)
|
||||
#define IPC_GET_PI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK)
|
||||
|
||||
#define IPC_SET_CI_FLAG(x) (x |= IPC_PI_CI_FLAG_MASK)
|
||||
#define IPC_RESET_CI_FLAG(x) (x &= IPC_PI_CI_INDEX_MASK)
|
||||
#define IPC_GET_CI_FLAG(x) (x >> 31)
|
||||
#define IPC_GET_CI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK)
|
||||
|
||||
/** buffer ring common metadata */
|
||||
typedef struct ipc_bd_ring_md {
|
||||
volatile uint32_t pi; /**< Producer index and flag (MSB)
|
||||
@ -180,6 +199,24 @@ struct bbdev_ipc_enqueue_op {
|
||||
uint32_t rsvd;
|
||||
};
|
||||
|
||||
/** Structure specifying dequeue operation (dequeue at LA1224) */
|
||||
struct bbdev_ipc_dequeue_op {
|
||||
/** Input buffer memory address */
|
||||
uint32_t in_addr;
|
||||
/** Input buffer memory length */
|
||||
uint32_t in_len;
|
||||
/** Output buffer memory address */
|
||||
uint32_t out_addr;
|
||||
/** Output buffer memory length */
|
||||
uint32_t out_len;
|
||||
/* Number of code blocks. Only set when HARQ is used */
|
||||
uint32_t num_code_blocks;
|
||||
/** Dequeue Operation flags */
|
||||
uint32_t op_flags;
|
||||
/** Shared metadata between L1 and L2 */
|
||||
uint32_t shared_metadata;
|
||||
};
|
||||
|
||||
/* This shared memory would be on the host side which have copy of some
|
||||
* of the parameters which are also part of Shared BD ring. Read access
|
||||
* of these parameters from the host side would not be over PCI.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user