common/qat: update firmware headers
Updated to latest firmware headers files for QuickAssist devices. Includes updates for symmetric crypto, PKE and Compression services. Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
This commit is contained in:
Fiona Trahe
Pablo de Lara
parent
711f43ba56
commit
b769101307
@ -117,6 +117,10 @@ struct icp_qat_fw_comn_resp {
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#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
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#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
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#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
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#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
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#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
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#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
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#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
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#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
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icp_qat_fw_comn_req_hdr_t.service_type
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@ -133,6 +137,16 @@ struct icp_qat_fw_comn_resp {
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#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
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ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
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#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
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QAT_FIELD_GET(hdr_flags, \
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ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
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ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
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#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
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QAT_FIELD_GET(hdr_flags, \
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ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
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ICP_QAT_FW_COMN_CNV_FLAG_MASK)
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#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
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ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
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@ -204,29 +218,44 @@ struct icp_qat_fw_comn_resp {
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& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
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((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
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#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
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do { \
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(next_curr_id) = \
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(((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
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(((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
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ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
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} while (0)
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#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
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do { \
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(next_curr_id) = \
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(((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
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((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \
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} while (0)
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#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
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#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
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#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
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#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
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#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
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#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
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#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
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#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
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#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
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#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
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#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
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((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
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QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
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(((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
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QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
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(((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
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QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
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(((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
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QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
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#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
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#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
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#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
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#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
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#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
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QAT_COMN_RESP_CRYPTO_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
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QAT_COMN_RESP_PKE_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
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QAT_COMN_RESP_CMP_STATUS_MASK)
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@ -235,10 +264,18 @@ struct icp_qat_fw_comn_resp {
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QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
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QAT_COMN_RESP_XLAT_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
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QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
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#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
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QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
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#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
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QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
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#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
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#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
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#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
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@ -257,8 +294,16 @@ struct icp_qat_fw_comn_resp {
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#define ERR_CODE_OVERFLOW_ERROR -11
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#define ERR_CODE_SOFT_ERROR -12
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#define ERR_CODE_FATAL_ERROR -13
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#define ERR_CODE_SSM_ERROR -14
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#define ERR_CODE_ENDPOINT_ERROR -15
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#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
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#define ERR_CODE_HW_INCOMPLETE_FILE -15
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#define ERR_CODE_SSM_ERROR -16
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#define ERR_CODE_ENDPOINT_ERROR -17
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#define ERR_CODE_CNV_ERROR -18
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#define ERR_CODE_EMPTY_DYM_BLOCK -19
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#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
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#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
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#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
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#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
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enum icp_qat_fw_slice {
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ICP_QAT_FW_SLICE_NULL = 0,
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482
drivers/common/qat/qat_adf/icp_qat_fw_comp.h
Normal file
482
drivers/common/qat/qat_adf/icp_qat_fw_comp.h
Normal file
@ -0,0 +1,482 @@
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/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
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* Copyright(c) 2015-2018 Intel Corporation
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*/
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#ifndef _ICP_QAT_FW_COMP_H_
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#define _ICP_QAT_FW_COMP_H_
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#include "icp_qat_fw.h"
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enum icp_qat_fw_comp_cmd_id {
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ICP_QAT_FW_COMP_CMD_STATIC = 0,
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/*!< Static Compress Request */
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ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
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/*!< Dynamic Compress Request */
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ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
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/*!< Decompress Request */
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ICP_QAT_FW_COMP_CMD_DELIMITER
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/**< Delimiter type */
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};
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/**< Flag usage */
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#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that session is stateless
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*/
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#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that session is stateful
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*/
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#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that autoselectbest is NOT used
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*/
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#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that autoselectbest is used
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*/
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#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that enhanced autoselectbest is NOT used
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*/
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#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that enhanced autoselectbest is used
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*/
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#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that enhanced autoselectbest is NOT used
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*/
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#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that enhanced autoselectbest is used
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*/
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#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
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/**< @ingroup icp_qat_fw_comp
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* Flag representing secure RAM from being used as
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* an intermediate buffer is DISABLED.
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*/
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#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
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/**< @ingroup icp_qat_fw_comp
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* Flag representing secure RAM from being used as
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* an intermediate buffer is ENABLED.
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*/
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/**< Flag mask & bit position */
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#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
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/**< @ingroup icp_qat_fw_comp
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* Starting bit position for the session type
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*/
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#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
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/**< @ingroup icp_qat_fw_comp
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* One bit mask used to determine the session type
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*/
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#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
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/**< @ingroup icp_qat_fw_comp
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* Starting bit position for auto select best
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*/
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#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
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/**< @ingroup icp_qat_fw_comp
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* One bit mask for auto select best
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*/
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#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
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/**< @ingroup icp_qat_fw_comp
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* Starting bit position for enhanced auto select best
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*/
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#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
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/**< @ingroup icp_qat_fw_comp
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* One bit mask for enhanced auto select best
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*/
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#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
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/**< @ingroup icp_qat_fw_comp
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* Starting bit position for disabling type zero header write back
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* when Enhanced autoselect best is enabled. If set firmware does
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* not return type0 store block header, only copies src to dest.
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* (if best output is Type0)
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*/
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#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
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/**< @ingroup icp_qat_fw_comp
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* One bit mask for auto select best
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*/
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#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
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/**< @ingroup icp_qat_fw_comp
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* Starting bit position for flag used to disable secure ram from
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* being used as an intermediate buffer.
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*/
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#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
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/**< @ingroup icp_qat_fw_comp
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* One bit mask for disable secure ram for use as an intermediate
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* buffer.
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*/
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#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
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ret_uncomp, secure_ram) \
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((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
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<< ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
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(((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
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<< ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
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(((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
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<< ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
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(((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
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<< ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
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(((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
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<< ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
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union icp_qat_fw_comp_req_hdr_cd_pars {
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/**< LWs 2-5 */
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struct {
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uint64_t content_desc_addr;
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/**< Address of the content descriptor */
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uint16_t content_desc_resrvd1;
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/**< Content descriptor reserved field */
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uint8_t content_desc_params_sz;
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/**< Size of the content descriptor parameters in quad words.
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* These parameters describe the session setup configuration
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* info for the slices that this request relies upon i.e.
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* the configuration word and cipher key needed by the cipher
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* slice if there is a request for cipher processing.
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*/
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uint8_t content_desc_hdr_resrvd2;
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/**< Content descriptor reserved field */
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uint32_t content_desc_resrvd3;
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/**< Content descriptor reserved field */
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} s;
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struct {
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uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
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/* Compression Slice Config Word */
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uint32_t content_desc_resrvd4;
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/**< Content descriptor reserved field */
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} sl;
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};
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struct icp_qat_fw_comp_req_params {
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/**< LW 14 */
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uint32_t comp_len;
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/**< Size of input to process in bytes Note: Only EOP requests can be
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* odd for decompression. IA must set LSB to zero for odd sized
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* intermediate inputs
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*/
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/**< LW 15 */
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uint32_t out_buffer_sz;
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/**< Size of output buffer in bytes */
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/**< LW 16 */
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uint32_t initial_crc32;
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/**< CRC of previously processed bytes */
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/**< LW 17 */
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uint32_t initial_adler;
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/**< Adler of previously processed bytes */
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/**< LW 18 */
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uint32_t req_par_flags;
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/**< LW 19 */
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uint32_t rsrvd;
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};
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#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \
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((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
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(((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
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(((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
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<< ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
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((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \
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((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \
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<< ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
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#define ICP_QAT_FW_COMP_NOT_SOP 0
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that a request is NOT Start of Packet
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*/
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#define ICP_QAT_FW_COMP_SOP 1
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that a request IS Start of Packet
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*/
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#define ICP_QAT_FW_COMP_NOT_EOP 0
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that a request is NOT Start of Packet
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*/
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#define ICP_QAT_FW_COMP_EOP 1
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/**< @ingroup icp_qat_fw_comp
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* Flag representing that a request IS End of Packet
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*/
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#define ICP_QAT_FW_COMP_NOT_BFINAL 0
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/**< @ingroup icp_qat_fw_comp
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* Flag representing to indicate firmware this is not the last block
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*/
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#define ICP_QAT_FW_COMP_BFINAL 1
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/**< @ingroup icp_qat_fw_comp
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* Flag representing to indicate firmware this is the last block
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*/
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#define ICP_QAT_FW_COMP_NO_CNV 0
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/**< @ingroup icp_qat_fw_comp
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* Flag indicating that NO cnv check is to be performed on the request
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*/
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#define ICP_QAT_FW_COMP_CNV 1
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/**< @ingroup icp_qat_fw_comp
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* Flag indicating that a cnv check IS to be performed on the request
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*/
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#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* Flag indicating that NO cnv recovery is to be performed on the request
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* Flag indicating that a cnv recovery is to be performed on the request
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_SOP_BITPOS 0
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* Starting bit position for SOP
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_SOP_MASK 0x1
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* One bit mask used to determine SOP
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_EOP_BITPOS 1
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* Starting bit position for EOP
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_EOP_MASK 0x1
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* One bit mask used to determine EOP
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* One bit mask for the bfinal bit
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* Starting bit position for the bfinal bit
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_CNV_MASK 0x1
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* One bit mask for the CNV bit
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_CNV_BITPOS 16
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* Starting bit position for the CNV bit
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* One bit mask for the CNV Recovery bit
|
||||
*/
|
||||
|
||||
#define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
|
||||
/**< @ingroup icp_qat_fw_comp
|
||||
* Starting bit position for the CNV Recovery bit
|
||||
*/
|
||||
|
||||
struct icp_qat_fw_xlt_req_params {
|
||||
/**< LWs 20-21 */
|
||||
uint64_t inter_buff_ptr;
|
||||
/**< This field specifies the physical address of an intermediate
|
||||
* buffer SGL array. The array contains a pair of 64-bit
|
||||
* intermediate buffer pointers to SGL buffer descriptors, one pair
|
||||
* per CPM. Please refer to the CPM1.6 Firmware Interface HLD
|
||||
* specification for more details.
|
||||
*/
|
||||
};
|
||||
|
||||
|
||||
struct icp_qat_fw_comp_cd_hdr {
|
||||
/**< LW 24 */
|
||||
uint16_t ram_bank_flags;
|
||||
/**< Flags to show which ram banks to access */
|
||||
|
||||
uint8_t comp_cfg_offset;
|
||||
/**< Quad word offset from the content descriptor parameters address
|
||||
* to the parameters for the compression processing
|
||||
*/
|
||||
|
||||
uint8_t next_curr_id;
|
||||
/**< This field combines the next and current id (each four bits) -
|
||||
* the next id is the most significant nibble.
|
||||
* Next Id: Set to the next slice to pass the compressed data through.
|
||||
* Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
|
||||
* anymore slices after compression
|
||||
* Current Id: Initialised with the compression slice type
|
||||
*/
|
||||
|
||||
/**< LW 25 */
|
||||
uint32_t resrvd;
|
||||
/**< LWs 26-27 */
|
||||
|
||||
uint64_t comp_state_addr;
|
||||
/**< Pointer to compression state */
|
||||
|
||||
/**< LWs 28-29 */
|
||||
uint64_t ram_banks_addr;
|
||||
/**< Pointer to banks */
|
||||
|
||||
};
|
||||
|
||||
|
||||
struct icp_qat_fw_xlt_cd_hdr {
|
||||
/**< LW 30 */
|
||||
uint16_t resrvd1;
|
||||
/**< Reserved field and assumed set to 0 */
|
||||
|
||||
uint8_t resrvd2;
|
||||
/**< Reserved field and assumed set to 0 */
|
||||
|
||||
uint8_t next_curr_id;
|
||||
/**< This field combines the next and current id (each four bits) -
|
||||
* the next id is the most significant nibble.
|
||||
* Next Id: Set to the next slice to pass the translated data through.
|
||||
* Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
|
||||
* any more slices after compression
|
||||
* Current Id: Initialised with the translation slice type
|
||||
*/
|
||||
|
||||
/**< LW 31 */
|
||||
uint32_t resrvd3;
|
||||
/**< Reserved and should be set to zero, needed for quadword
|
||||
* alignment
|
||||
*/
|
||||
};
|
||||
|
||||
struct icp_qat_fw_comp_req {
|
||||
/**< LWs 0-1 */
|
||||
struct icp_qat_fw_comn_req_hdr comn_hdr;
|
||||
/**< Common request header - for Service Command Id,
|
||||
* use service-specific Compression Command Id.
|
||||
* Service Specific Flags - use Compression Command Flags
|
||||
*/
|
||||
|
||||
/**< LWs 2-5 */
|
||||
union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
|
||||
/**< Compression service-specific content descriptor field which points
|
||||
* either to a content descriptor parameter block or contains the
|
||||
* compression slice config word.
|
||||
*/
|
||||
|
||||
/**< LWs 6-13 */
|
||||
struct icp_qat_fw_comn_req_mid comn_mid;
|
||||
/**< Common request middle section */
|
||||
|
||||
/**< LWs 14-19 */
|
||||
struct icp_qat_fw_comp_req_params comp_pars;
|
||||
/**< Compression request Parameters block */
|
||||
|
||||
/**< LWs 20-21 */
|
||||
union {
|
||||
struct icp_qat_fw_xlt_req_params xlt_pars;
|
||||
/**< Translation request Parameters block */
|
||||
uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
|
||||
/**< Reserved if not used for translation */
|
||||
|
||||
} u1;
|
||||
|
||||
/**< LWs 22-23 */
|
||||
union {
|
||||
uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
|
||||
/**< Reserved - not used if Batch and Pack is disabled.*/
|
||||
|
||||
uint64_t bnp_res_table_addr;
|
||||
/**< A generic pointer to the unbounded list of
|
||||
* icp_qat_fw_resp_comp_pars members. This pointer is only
|
||||
* used when the Batch and Pack is enabled.
|
||||
*/
|
||||
} u3;
|
||||
|
||||
/**< LWs 24-29 */
|
||||
struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
|
||||
/**< Compression request content descriptor control block header */
|
||||
|
||||
/**< LWs 30-31 */
|
||||
union {
|
||||
struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
|
||||
/**< Translation request content descriptor
|
||||
* control block header
|
||||
*/
|
||||
|
||||
uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
|
||||
/**< Reserved if not used for translation */
|
||||
} u2;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_resp_comp_pars {
|
||||
/**< LW 4 */
|
||||
uint32_t input_byte_counter;
|
||||
/**< Input byte counter */
|
||||
|
||||
/**< LW 5 */
|
||||
uint32_t output_byte_counter;
|
||||
/**< Output byte counter */
|
||||
|
||||
/**< LW 6 & 7*/
|
||||
union {
|
||||
uint64_t curr_chksum;
|
||||
struct {
|
||||
/**< LW 6 */
|
||||
uint32_t curr_crc32;
|
||||
/**< LW 7 */
|
||||
uint32_t curr_adler_32;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct icp_qat_fw_comp_resp {
|
||||
/**< LWs 0-1 */
|
||||
struct icp_qat_fw_comn_resp_hdr comn_resp;
|
||||
/**< Common interface response format see icp_qat_fw.h */
|
||||
|
||||
/**< LWs 2-3 */
|
||||
uint64_t opaque_data;
|
||||
/**< Opaque data passed from the request to the response message */
|
||||
|
||||
/**< LWs 4-7 */
|
||||
struct icp_qat_fw_resp_comp_pars comp_resp_pars;
|
||||
/**< Common response params (checksums and byte counts) */
|
||||
};
|
||||
|
||||
#endif
|
||||
@ -72,19 +72,44 @@ struct icp_qat_hw_auth_config {
|
||||
#define QAT_AUTH_ALGO_MASK 0xF
|
||||
#define QAT_AUTH_CMP_BITPOS 8
|
||||
#define QAT_AUTH_CMP_MASK 0x7F
|
||||
#define QAT_AUTH_SHA3_PADDING_BITPOS 16
|
||||
#define QAT_AUTH_SHA3_PADDING_MASK 0x1
|
||||
#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
|
||||
#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
|
||||
#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
|
||||
#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
|
||||
#define QAT_AUTH_ALGO_SHA3_BITPOS 22
|
||||
#define QAT_AUTH_ALGO_SHA3_MASK 0x3
|
||||
#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
|
||||
(((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
|
||||
((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
|
||||
(((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
|
||||
QAT_AUTH_ALGO_SHA3_BITPOS) | \
|
||||
(((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
|
||||
(algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
|
||||
& QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
|
||||
((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
|
||||
#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
|
||||
#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
|
||||
#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
|
||||
#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
|
||||
#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
|
||||
#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
|
||||
#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
|
||||
#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
|
||||
#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
|
||||
#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
|
||||
#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
|
||||
|
||||
#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
|
||||
((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
|
||||
(((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
|
||||
(((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \
|
||||
<< QAT_AUTH_ALGO_SHA3_BITPOS) | \
|
||||
(((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \
|
||||
QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \
|
||||
<< QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \
|
||||
(((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \
|
||||
QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \
|
||||
<< QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \
|
||||
(((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
|
||||
|
||||
#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \
|
||||
((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \
|
||||
QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \
|
||||
<< QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \
|
||||
(((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \
|
||||
QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \
|
||||
<< QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
|
||||
|
||||
struct icp_qat_hw_auth_counter {
|
||||
uint32_t counter;
|
||||
@ -107,13 +132,13 @@ struct icp_qat_hw_auth_setup {
|
||||
#define ICP_QAT_HW_MD5_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_SHA1_STATE1_SZ 20
|
||||
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
|
||||
#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
|
||||
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
|
||||
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
|
||||
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
|
||||
#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
|
||||
#define ICP_QAT_HW_SHA512_STATE1_SZ 64
|
||||
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
|
||||
#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
|
||||
#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
|
||||
#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
|
||||
@ -121,17 +146,18 @@ struct icp_qat_hw_auth_setup {
|
||||
#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
|
||||
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
|
||||
|
||||
#define ICP_QAT_HW_NULL_STATE2_SZ 32
|
||||
#define ICP_QAT_HW_MD5_STATE2_SZ 16
|
||||
#define ICP_QAT_HW_SHA1_STATE2_SZ 20
|
||||
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
|
||||
#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
|
||||
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
|
||||
#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_SHA512_STATE2_SZ 64
|
||||
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
|
||||
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
|
||||
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
|
||||
@ -154,6 +180,12 @@ struct icp_qat_hw_auth_sha512 {
|
||||
uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
|
||||
};
|
||||
|
||||
struct icp_qat_hw_auth_sha3_512 {
|
||||
struct icp_qat_hw_auth_setup inner_setup;
|
||||
uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
|
||||
struct icp_qat_hw_auth_setup outer_setup;
|
||||
};
|
||||
|
||||
struct icp_qat_hw_auth_algo_blk {
|
||||
struct icp_qat_hw_auth_sha512 sha;
|
||||
};
|
||||
@ -283,4 +315,72 @@ struct icp_qat_hw_cipher_algo_blk {
|
||||
uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
|
||||
} __rte_cache_aligned;
|
||||
|
||||
/* ========================================================================= */
|
||||
/* COMPRESSION SLICE */
|
||||
/* ========================================================================= */
|
||||
|
||||
enum icp_qat_hw_compression_direction {
|
||||
ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
|
||||
ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
|
||||
ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
|
||||
};
|
||||
|
||||
enum icp_qat_hw_compression_delayed_match {
|
||||
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
|
||||
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
|
||||
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
|
||||
};
|
||||
|
||||
enum icp_qat_hw_compression_algo {
|
||||
ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
|
||||
ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
|
||||
ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
|
||||
};
|
||||
|
||||
|
||||
enum icp_qat_hw_compression_depth {
|
||||
ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
|
||||
ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
|
||||
ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
|
||||
ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
|
||||
ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
|
||||
};
|
||||
|
||||
enum icp_qat_hw_compression_file_type {
|
||||
ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
|
||||
ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
|
||||
ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
|
||||
ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
|
||||
ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
|
||||
ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
|
||||
};
|
||||
|
||||
struct icp_qat_hw_compression_config {
|
||||
uint32_t val;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
#define QAT_COMPRESSION_DIR_BITPOS 4
|
||||
#define QAT_COMPRESSION_DIR_MASK 0x7
|
||||
#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
|
||||
#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
|
||||
#define QAT_COMPRESSION_ALGO_BITPOS 31
|
||||
#define QAT_COMPRESSION_ALGO_MASK 0x1
|
||||
#define QAT_COMPRESSION_DEPTH_BITPOS 28
|
||||
#define QAT_COMPRESSION_DEPTH_MASK 0x7
|
||||
#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
|
||||
#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
|
||||
|
||||
#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \
|
||||
dir, delayed, algo, depth, filetype) \
|
||||
((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
|
||||
(((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \
|
||||
<< QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
|
||||
(((algo) & QAT_COMPRESSION_ALGO_MASK) \
|
||||
<< QAT_COMPRESSION_ALGO_BITPOS) | \
|
||||
(((depth) & QAT_COMPRESSION_DEPTH_MASK) \
|
||||
<< QAT_COMPRESSION_DEPTH_BITPOS) | \
|
||||
(((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \
|
||||
<< QAT_COMPRESSION_FILE_TYPE_BITPOS))
|
||||
|
||||
#endif
|
||||
|
||||
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Reference in New Issue
Block a user