crypto/octeontx2: register security operations

This patch registers security operations with cryptodev.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
This commit is contained in:
Tejasree Kondoj 2020-07-16 14:09:27 +05:30 committed by Akhil Goyal
parent e6c1223dd5
commit b9765e96c2
6 changed files with 67 additions and 2 deletions

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@ -8,6 +8,7 @@ Symmetric crypto = Y
Asymmetric crypto = Y
Sym operation chaining = Y
HW Accelerated = Y
Protocol offload = Y
In Place SGL = Y
OOP SGL In LB Out = Y
OOP SGL In SGL Out = Y

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@ -38,6 +38,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_capabilities.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_sec.c
# export include files
SYMLINK-y-include +=

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@ -17,7 +17,8 @@ sources = files('otx2_cryptodev.c',
'otx2_cryptodev_capabilities.c',
'otx2_cryptodev_hw_access.c',
'otx2_cryptodev_mbox.c',
'otx2_cryptodev_ops.c')
'otx2_cryptodev_ops.c',
'otx2_cryptodev_sec.c')
extra_flags = []
# This integrated controller runs only on a arm64 machine, remove 32bit warnings

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@ -17,6 +17,7 @@
#include "otx2_cryptodev_capabilities.h"
#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
#include "otx2_cryptodev_sec.h"
#include "otx2_dev.h"
/* CPT common headers */
@ -103,6 +104,11 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
otx2_crypto_capabilities_init(vf->hw_caps);
/* Create security ctx */
ret = otx2_crypto_sec_ctx_create(dev);
if (ret)
goto otx2_dev_fini;
dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
RTE_CRYPTODEV_FF_HW_ACCELERATED |
RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
@ -111,7 +117,8 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |
RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT |
RTE_CRYPTODEV_FF_SYM_SESSIONLESS;
RTE_CRYPTODEV_FF_SYM_SESSIONLESS |
RTE_CRYPTODEV_FF_SECURITY;
return 0;
@ -140,6 +147,9 @@ otx2_cpt_pci_remove(struct rte_pci_device *pci_dev)
if (dev == NULL)
return -ENODEV;
/* Destroy security ctx */
otx2_crypto_sec_ctx_destroy(dev);
return rte_cryptodev_pmd_destroy(dev);
}

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@ -0,0 +1,46 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright (C) 2020 Marvell International Ltd.
*/
#include <rte_cryptodev.h>
#include <rte_malloc.h>
#include <rte_security.h>
#include <rte_security_driver.h>
#include "otx2_cryptodev_sec.h"
static struct rte_security_ops otx2_crypto_sec_ops = {
.session_create = NULL,
.session_destroy = NULL,
.session_get_size = NULL,
.set_pkt_metadata = NULL,
.get_userdata = NULL,
.capabilities_get = NULL
};
int
otx2_crypto_sec_ctx_create(struct rte_cryptodev *cdev)
{
struct rte_security_ctx *ctx;
ctx = rte_malloc("otx2_cpt_dev_sec_ctx",
sizeof(struct rte_security_ctx), 0);
if (ctx == NULL)
return -ENOMEM;
/* Populate ctx */
ctx->device = cdev;
ctx->ops = &otx2_crypto_sec_ops;
ctx->sess_cnt = 0;
cdev->security_ctx = ctx;
return 0;
}
void
otx2_crypto_sec_ctx_destroy(struct rte_cryptodev *cdev)
{
rte_free(cdev->security_ctx);
}

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@ -5,6 +5,8 @@
#ifndef __OTX2_CRYPTODEV_SEC_H__
#define __OTX2_CRYPTODEV_SEC_H__
#include <rte_cryptodev.h>
#include "otx2_ipsec_po.h"
struct otx2_sec_session_ipsec_lp {
@ -55,4 +57,8 @@ struct otx2_sec_session_ipsec_lp {
uint8_t auth_iv_length;
};
int otx2_crypto_sec_ctx_create(struct rte_cryptodev *crypto_dev);
void otx2_crypto_sec_ctx_destroy(struct rte_cryptodev *crypto_dev);
#endif /* __OTX2_CRYPTODEV_SEC_H__ */