common/sfc_efx/base: add event queue module for Riverhead
Events are significantly reworked on Riverhead, so it is better to implement own set of callbacks to simplify future development and avoid inheritance of legacy code. Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com> Reviewed-by: Andy Moreton <amoreton@xilinx.com>
This commit is contained in:
Andrew Rybchenko
Ferruh Yigit
parent
8aad114949
commit
b97bf1cac2
@ -109,6 +109,22 @@ static const efx_ev_ops_t __efx_ev_ef10_ops = {
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};
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#endif /* EFX_OPTS_EF10() */
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#if EFSYS_OPT_RIVERHEAD
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static const efx_ev_ops_t __efx_ev_rhead_ops = {
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rhead_ev_init, /* eevo_init */
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rhead_ev_fini, /* eevo_fini */
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rhead_ev_qcreate, /* eevo_qcreate */
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rhead_ev_qdestroy, /* eevo_qdestroy */
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rhead_ev_qprime, /* eevo_qprime */
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rhead_ev_qpost, /* eevo_qpost */
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rhead_ev_qpoll, /* eevo_qpoll */
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rhead_ev_qmoderate, /* eevo_qmoderate */
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#if EFSYS_OPT_QSTATS
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rhead_ev_qstats_update, /* eevo_qstats_update */
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#endif
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};
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#endif /* EFSYS_OPT_RIVERHEAD */
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__checkReturn efx_rc_t
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efx_ev_init(
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@ -150,6 +166,12 @@ efx_ev_init(
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break;
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#endif /* EFSYS_OPT_MEDFORD2 */
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#if EFSYS_OPT_RIVERHEAD
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case EFX_FAMILY_RIVERHEAD:
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eevop = &__efx_ev_rhead_ops;
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break;
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#endif /* EFSYS_OPT_RIVERHEAD */
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default:
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EFSYS_ASSERT(0);
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rc = ENOTSUP;
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@ -1408,7 +1408,7 @@ efx_mcdi_get_workarounds(
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__out_opt uint32_t *implementedp,
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__out_opt uint32_t *enabledp);
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#if EFX_OPTS_EF10()
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#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
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LIBEFX_INTERNAL
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extern __checkReturn efx_rc_t
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@ -1428,7 +1428,7 @@ efx_mcdi_fini_evq(
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__in efx_nic_t *enp,
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__in uint32_t instance);
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#endif /* EFX_OPTS_EF10() */
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#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
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#endif /* EFSYS_OPT_MCDI */
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@ -2443,7 +2443,20 @@ fail1:
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return (rc);
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}
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#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
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#define INIT_EVQ_MAXNBUFS MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM
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#if EFX_OPTS_EF10()
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# if (INIT_EVQ_MAXNBUFS < EF10_EVQ_MAXNBUFS)
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# error "INIT_EVQ_MAXNBUFS too small"
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# endif
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#endif /* EFX_OPTS_EF10 */
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#if EFSYS_OPT_RIVERHEAD
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# if (INIT_EVQ_MAXNBUFS < RHEAD_EVQ_MAXNBUFS)
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# error "INIT_EVQ_MAXNBUFS too small"
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# endif
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#endif /* EFSYS_OPT_RIVERHEAD */
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__checkReturn efx_rc_t
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efx_mcdi_init_evq(
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@ -2459,7 +2472,7 @@ efx_mcdi_init_evq(
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const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
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efx_mcdi_req_t req;
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EFX_MCDI_DECLARE_BUF(payload,
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MC_CMD_INIT_EVQ_V2_IN_LEN(EF10_EVQ_MAXNBUFS),
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MC_CMD_INIT_EVQ_V2_IN_LEN(INIT_EVQ_MAXNBUFS),
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MC_CMD_INIT_EVQ_V2_OUT_LEN);
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boolean_t interrupting;
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int ev_cut_through;
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@ -2472,7 +2485,7 @@ efx_mcdi_init_evq(
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efx_rc_t rc;
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npages = efx_evq_nbufs(enp, nevs);
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if (npages > EF10_EVQ_MAXNBUFS) {
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if (npages > INIT_EVQ_MAXNBUFS) {
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rc = EINVAL;
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goto fail1;
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}
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@ -2667,6 +2680,6 @@ fail1:
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return (rc);
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}
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#endif /* EFX_OPTS_EF10() */
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#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
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#endif /* EFSYS_OPT_MCDI */
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@ -52,6 +52,7 @@ sources = [
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'hunt_nic.c',
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'medford_nic.c',
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'medford2_nic.c',
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'rhead_ev.c',
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'rhead_intr.c',
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'rhead_nic.c',
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]
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265
drivers/common/sfc_efx/base/rhead_ev.c
Normal file
265
drivers/common/sfc_efx/base/rhead_ev.c
Normal file
@ -0,0 +1,265 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright(c) 2019-2020 Xilinx, Inc.
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* Copyright(c) 2018-2019 Solarflare Communications Inc.
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*/
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#include "efx.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_RIVERHEAD
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/*
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* Non-interrupting event queue requires interrupting event queue to
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* refer to for wake-up events even if wake ups are never used.
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* It could be even non-allocated event queue.
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*/
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#define EFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
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__checkReturn efx_rc_t
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rhead_ev_init(
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__in efx_nic_t *enp)
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{
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_NOTE(ARGUNUSED(enp))
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return (0);
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}
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void
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rhead_ev_fini(
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__in efx_nic_t *enp)
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{
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_NOTE(ARGUNUSED(enp))
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}
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__checkReturn efx_rc_t
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rhead_ev_qcreate(
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__in efx_nic_t *enp,
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__in unsigned int index,
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__in efsys_mem_t *esmp,
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__in size_t ndescs,
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__in uint32_t id,
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__in uint32_t us,
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__in uint32_t flags,
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__in efx_evq_t *eep)
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{
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uint32_t irq;
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efx_rc_t rc;
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_NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
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/* Set up the handler table */
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eep->ee_rx = NULL; /* FIXME */
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eep->ee_tx = NULL; /* FIXME */
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eep->ee_driver = NULL; /* FIXME */
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eep->ee_drv_gen = NULL; /* FIXME */
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eep->ee_mcdi = NULL; /* FIXME */
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/* Set up the event queue */
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/* INIT_EVQ expects function-relative vector number */
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if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
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EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
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irq = index;
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} else if (index == EFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX) {
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irq = index;
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flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
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EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
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} else {
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irq = EFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX;
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}
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/*
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* Interrupts may be raised for events immediately after the queue is
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* created. See bug58606.
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*/
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rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
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B_FALSE);
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if (rc != 0)
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goto fail1;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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void
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rhead_ev_qdestroy(
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__in efx_evq_t *eep)
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{
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efx_nic_t *enp = eep->ee_enp;
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EFSYS_ASSERT(enp->en_family == EFX_FAMILY_RIVERHEAD);
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(void) efx_mcdi_fini_evq(enp, eep->ee_index);
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}
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__checkReturn efx_rc_t
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rhead_ev_qprime(
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__in efx_evq_t *eep,
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__in unsigned int count)
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{
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efx_nic_t *enp = eep->ee_enp;
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uint32_t rptr;
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efx_dword_t dword;
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rptr = count & eep->ee_mask;
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EFX_POPULATE_DWORD_2(dword, ERF_GZ_EVQ_ID, eep->ee_index,
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ERF_GZ_IDX, rptr);
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/* EVQ_INT_PRIME lives function control window only on Riverhead */
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EFX_BAR_WRITED(enp, ER_GZ_EVQ_INT_PRIME, &dword, B_FALSE);
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return (0);
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}
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void
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rhead_ev_qpost(
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__in efx_evq_t *eep,
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__in uint16_t data)
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{
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_NOTE(ARGUNUSED(eep, data))
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/* Not implemented yet */
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EFSYS_ASSERT(B_FALSE);
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}
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/*
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* Poll event queue in batches. Size of the batch is equal to cache line
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* size divided by event size.
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*
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* Event queue is written by NIC and read by CPU. If CPU starts reading
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* of events on the cache line, read all remaining events in a tight
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* loop while event is present.
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*/
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#define EF100_EV_BATCH 8
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/*
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* Check if event is present.
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*
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* Riverhead EvQs use a phase bit to indicate the presence of valid events,
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* by flipping the phase bit on each wrap of the write index.
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*/
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#define EF100_EV_PRESENT(_qword, _phase_bit) \
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(EFX_QWORD_FIELD((_qword), ESF_GZ_EV_EVQ_PHASE) == _phase_bit)
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void
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rhead_ev_qpoll(
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__in efx_evq_t *eep,
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__inout unsigned int *countp,
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__in const efx_ev_callbacks_t *eecp,
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__in_opt void *arg)
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{
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efx_qword_t ev[EF100_EV_BATCH];
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unsigned int batch;
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unsigned int phase_bit;
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unsigned int total;
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unsigned int count;
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unsigned int index;
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size_t offset;
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EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
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EFSYS_ASSERT(countp != NULL);
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EFSYS_ASSERT(eecp != NULL);
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count = *countp;
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do {
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/* Read up until the end of the batch period */
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batch = EF100_EV_BATCH - (count & (EF100_EV_BATCH - 1));
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phase_bit = (count & (eep->ee_mask + 1)) != 0;
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offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
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for (total = 0; total < batch; ++total) {
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EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
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if (!EF100_EV_PRESENT(ev[total], phase_bit))
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break;
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EFSYS_PROBE3(event, unsigned int, eep->ee_index,
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uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
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uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
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offset += sizeof (efx_qword_t);
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}
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/* Process the batch of events */
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for (index = 0; index < total; ++index) {
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boolean_t should_abort;
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uint32_t code;
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EFX_EV_QSTAT_INCR(eep, EV_ALL);
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code = EFX_QWORD_FIELD(ev[index], ESF_GZ_E_TYPE);
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switch (code) {
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default:
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EFSYS_PROBE3(bad_event,
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unsigned int, eep->ee_index,
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uint32_t,
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EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
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uint32_t,
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EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
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EFSYS_ASSERT(eecp->eec_exception != NULL);
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(void) eecp->eec_exception(arg,
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EFX_EXCEPTION_EV_ERROR, code);
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should_abort = B_TRUE;
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}
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if (should_abort) {
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/* Ignore subsequent events */
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total = index + 1;
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/*
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* Poison batch to ensure the outer
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* loop is broken out of.
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*/
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EFSYS_ASSERT(batch <= EF100_EV_BATCH);
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batch += (EF100_EV_BATCH << 1);
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EFSYS_ASSERT(total != batch);
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break;
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}
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}
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/*
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* There is no necessity to clear processed events since
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* phase bit which is flipping on each write index wrap
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* is used for event presence indication.
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*/
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count += total;
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} while (total == batch);
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*countp = count;
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}
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__checkReturn efx_rc_t
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rhead_ev_qmoderate(
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__in efx_evq_t *eep,
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__in unsigned int us)
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{
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_NOTE(ARGUNUSED(eep, us))
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return (ENOTSUP);
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}
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#if EFSYS_OPT_QSTATS
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void
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rhead_ev_qstats_update(
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__in efx_evq_t *eep,
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__inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
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{
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unsigned int id;
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for (id = 0; id < EV_NQSTATS; id++) {
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efsys_stat_t *essp = &stat[id];
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EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
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eep->ee_stat[id] = 0;
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}
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}
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#endif /* EFSYS_OPT_QSTATS */
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#endif /* EFSYS_OPT_RIVERHEAD */
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@ -12,6 +12,13 @@ extern "C" {
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#endif
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/*
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* Riverhead requires physically contiguous event rings (so, just one
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* DMA address is sufficient to represent it), but MCDI interface is still
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* in terms of 4k size 4k-aligned DMA buffers.
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*/
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#define RHEAD_EVQ_MAXNBUFS 32
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#define RHEAD_EVQ_MAXNEVS 16384
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#define RHEAD_EVQ_MINNEVS 256
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@ -98,6 +105,72 @@ rhead_nic_unprobe(
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__in efx_nic_t *enp);
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/* EV */
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LIBEFX_INTERNAL
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extern __checkReturn efx_rc_t
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rhead_ev_init(
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__in efx_nic_t *enp);
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LIBEFX_INTERNAL
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extern void
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rhead_ev_fini(
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__in efx_nic_t *enp);
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LIBEFX_INTERNAL
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extern __checkReturn efx_rc_t
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rhead_ev_qcreate(
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__in efx_nic_t *enp,
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__in unsigned int index,
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__in efsys_mem_t *esmp,
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__in size_t ndescs,
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__in uint32_t id,
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__in uint32_t us,
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__in uint32_t flags,
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__in efx_evq_t *eep);
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LIBEFX_INTERNAL
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extern void
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rhead_ev_qdestroy(
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__in efx_evq_t *eep);
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LIBEFX_INTERNAL
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extern __checkReturn efx_rc_t
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rhead_ev_qprime(
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__in efx_evq_t *eep,
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__in unsigned int count);
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LIBEFX_INTERNAL
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extern void
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rhead_ev_qpost(
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__in efx_evq_t *eep,
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__in uint16_t data);
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LIBEFX_INTERNAL
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extern void
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rhead_ev_qpoll(
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__in efx_evq_t *eep,
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__inout unsigned int *countp,
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__in const efx_ev_callbacks_t *eecp,
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__in_opt void *arg);
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LIBEFX_INTERNAL
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extern __checkReturn efx_rc_t
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rhead_ev_qmoderate(
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__in efx_evq_t *eep,
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__in unsigned int us);
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#if EFSYS_OPT_QSTATS
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LIBEFX_INTERNAL
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extern void
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rhead_ev_qstats_update(
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__in efx_evq_t *eep,
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__inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
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#endif /* EFSYS_OPT_QSTATS */
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/* INTR */
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LIBEFX_INTERNAL
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