pipeline: introduce SWX add instruction
The add instruction source can be header field (H), meta-data field (M), extern object (E) or function (F) mailbox field, table entry action data field (T) or immediate value (I). The destination is HMEF. Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
This commit is contained in:
Cristian Dumitrescu
David Marchand
parent
8319c47c5f
commit
baf7999303
@ -267,6 +267,17 @@ enum instruction_type {
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INSTR_DMA_HT6,
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INSTR_DMA_HT7,
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INSTR_DMA_HT8,
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/* add dst src
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* dst += src
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* dst = HMEF, src = HMEFTI
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*/
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INSTR_ALU_ADD, /* dst = MEF, src = MEF */
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INSTR_ALU_ADD_MH, /* dst = MEF, src = H */
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INSTR_ALU_ADD_HM, /* dst = H, src = MEF */
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INSTR_ALU_ADD_HH, /* dst = H, src = H */
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INSTR_ALU_ADD_MI, /* dst = MEF, src = I */
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INSTR_ALU_ADD_HI, /* dst = H, src = I */
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};
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struct instr_operand {
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@ -322,6 +333,7 @@ struct instruction {
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struct instr_hdr_validity valid;
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struct instr_dst_src mov;
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struct instr_dma dma;
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struct instr_dst_src alu;
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};
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};
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@ -436,6 +448,136 @@ struct thread {
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#define MASK64_BIT_SET(mask, pos) ((mask) | (1LLU << (pos)))
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#define MASK64_BIT_CLR(mask, pos) ((mask) & ~(1LLU << (pos)))
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#define ALU(thread, ip, operator) \
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{ \
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uint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \
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uint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \
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uint64_t dst64 = *dst64_ptr; \
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uint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \
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uint64_t dst = dst64 & dst64_mask; \
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\
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uint8_t *src_struct = (thread)->structs[(ip)->alu.src.struct_id]; \
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uint64_t *src64_ptr = (uint64_t *)&src_struct[(ip)->alu.src.offset]; \
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uint64_t src64 = *src64_ptr; \
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uint64_t src64_mask = UINT64_MAX >> (64 - (ip)->alu.src.n_bits); \
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uint64_t src = src64 & src64_mask; \
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\
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uint64_t result = dst operator src; \
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\
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*dst64_ptr = (dst64 & ~dst64_mask) | (result & dst64_mask); \
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}
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#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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#define ALU_S(thread, ip, operator) \
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{ \
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uint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \
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uint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \
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uint64_t dst64 = *dst64_ptr; \
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uint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \
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uint64_t dst = dst64 & dst64_mask; \
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\
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uint8_t *src_struct = (thread)->structs[(ip)->alu.src.struct_id]; \
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uint64_t *src64_ptr = (uint64_t *)&src_struct[(ip)->alu.src.offset]; \
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uint64_t src64 = *src64_ptr; \
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uint64_t src = ntoh64(src64) >> (64 - (ip)->alu.src.n_bits); \
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\
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uint64_t result = dst operator src; \
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\
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*dst64_ptr = (dst64 & ~dst64_mask) | (result & dst64_mask); \
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}
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#define ALU_MH ALU_S
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#define ALU_HM(thread, ip, operator) \
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{ \
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uint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \
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uint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \
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uint64_t dst64 = *dst64_ptr; \
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uint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \
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uint64_t dst = ntoh64(dst64) >> (64 - (ip)->alu.dst.n_bits); \
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\
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uint8_t *src_struct = (thread)->structs[(ip)->alu.src.struct_id]; \
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uint64_t *src64_ptr = (uint64_t *)&src_struct[(ip)->alu.src.offset]; \
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uint64_t src64 = *src64_ptr; \
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uint64_t src64_mask = UINT64_MAX >> (64 - (ip)->alu.src.n_bits); \
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uint64_t src = src64 & src64_mask; \
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\
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uint64_t result = dst operator src; \
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result = hton64(result << (64 - (ip)->alu.dst.n_bits)); \
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\
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*dst64_ptr = (dst64 & ~dst64_mask) | result; \
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}
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#define ALU_HH(thread, ip, operator) \
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{ \
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uint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \
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uint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \
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uint64_t dst64 = *dst64_ptr; \
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uint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \
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uint64_t dst = ntoh64(dst64) >> (64 - (ip)->alu.dst.n_bits); \
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\
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uint8_t *src_struct = (thread)->structs[(ip)->alu.src.struct_id]; \
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uint64_t *src64_ptr = (uint64_t *)&src_struct[(ip)->alu.src.offset]; \
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uint64_t src64 = *src64_ptr; \
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uint64_t src = ntoh64(src64) >> (64 - (ip)->alu.src.n_bits); \
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\
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uint64_t result = dst operator src; \
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result = hton64(result << (64 - (ip)->alu.dst.n_bits)); \
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\
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*dst64_ptr = (dst64 & ~dst64_mask) | result; \
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}
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#else
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#define ALU_S ALU
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#define ALU_MH ALU
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#define ALU_HM ALU
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#define ALU_HH ALU
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#endif
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#define ALU_I(thread, ip, operator) \
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{ \
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uint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \
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uint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \
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uint64_t dst64 = *dst64_ptr; \
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uint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \
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uint64_t dst = dst64 & dst64_mask; \
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\
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uint64_t src = (ip)->alu.src_val; \
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\
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uint64_t result = dst operator src; \
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\
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*dst64_ptr = (dst64 & ~dst64_mask) | (result & dst64_mask); \
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}
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#define ALU_MI ALU_I
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#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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#define ALU_HI(thread, ip, operator) \
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{ \
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uint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \
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uint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \
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uint64_t dst64 = *dst64_ptr; \
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uint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \
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uint64_t dst = ntoh64(dst64) >> (64 - (ip)->alu.dst.n_bits); \
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\
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uint64_t src = (ip)->alu.src_val; \
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\
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uint64_t result = dst operator src; \
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result = hton64(result << (64 - (ip)->alu.dst.n_bits)); \
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\
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*dst64_ptr = (dst64 & ~dst64_mask) | result; \
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}
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#else
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#define ALU_HI ALU_I
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#endif
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#define MOV(thread, ip) \
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{ \
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uint8_t *dst_struct = (thread)->structs[(ip)->mov.dst.struct_id]; \
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@ -2719,6 +2861,151 @@ instr_dma_ht8_exec(struct rte_swx_pipeline *p)
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thread_ip_inc(p);
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}
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/*
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* alu.
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*/
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static int
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instr_alu_add_translate(struct rte_swx_pipeline *p,
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struct action *action,
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char **tokens,
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int n_tokens,
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struct instruction *instr,
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struct instruction_data *data __rte_unused)
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{
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char *dst = tokens[1], *src = tokens[2];
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struct field *fdst, *fsrc;
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uint32_t dst_struct_id, src_struct_id, src_val;
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CHECK(n_tokens == 3, EINVAL);
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fdst = struct_field_parse(p, NULL, dst, &dst_struct_id);
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CHECK(fdst, EINVAL);
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/* ADD, ADD_HM, ADD_MH, ADD_HH. */
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fsrc = struct_field_parse(p, action, src, &src_struct_id);
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if (fsrc) {
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instr->type = INSTR_ALU_ADD;
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if (dst[0] == 'h' && src[0] == 'm')
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instr->type = INSTR_ALU_ADD_HM;
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if (dst[0] == 'm' && src[0] == 'h')
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instr->type = INSTR_ALU_ADD_MH;
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if (dst[0] == 'h' && src[0] == 'h')
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instr->type = INSTR_ALU_ADD_HH;
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instr->alu.dst.struct_id = (uint8_t)dst_struct_id;
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instr->alu.dst.n_bits = fdst->n_bits;
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instr->alu.dst.offset = fdst->offset / 8;
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instr->alu.src.struct_id = (uint8_t)src_struct_id;
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instr->alu.src.n_bits = fsrc->n_bits;
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instr->alu.src.offset = fsrc->offset / 8;
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return 0;
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}
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/* ADD_MI, ADD_HI. */
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src_val = strtoul(src, &src, 0);
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CHECK(!src[0], EINVAL);
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instr->type = INSTR_ALU_ADD_MI;
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if (dst[0] == 'h')
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instr->type = INSTR_ALU_ADD_HI;
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instr->alu.dst.struct_id = (uint8_t)dst_struct_id;
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instr->alu.dst.n_bits = fdst->n_bits;
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instr->alu.dst.offset = fdst->offset / 8;
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instr->alu.src_val = (uint32_t)src_val;
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return 0;
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}
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static inline void
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instr_alu_add_exec(struct rte_swx_pipeline *p)
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{
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struct thread *t = &p->threads[p->thread_id];
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struct instruction *ip = t->ip;
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TRACE("[Thread %2u] add\n", p->thread_id);
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/* Structs. */
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ALU(t, ip, +);
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/* Thread. */
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thread_ip_inc(p);
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}
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static inline void
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instr_alu_add_mh_exec(struct rte_swx_pipeline *p)
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{
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struct thread *t = &p->threads[p->thread_id];
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struct instruction *ip = t->ip;
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TRACE("[Thread %2u] add (mh)\n", p->thread_id);
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/* Structs. */
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ALU_MH(t, ip, +);
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/* Thread. */
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thread_ip_inc(p);
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}
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static inline void
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instr_alu_add_hm_exec(struct rte_swx_pipeline *p)
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{
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struct thread *t = &p->threads[p->thread_id];
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struct instruction *ip = t->ip;
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TRACE("[Thread %2u] add (hm)\n", p->thread_id);
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/* Structs. */
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ALU_HM(t, ip, +);
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/* Thread. */
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thread_ip_inc(p);
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}
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static inline void
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instr_alu_add_hh_exec(struct rte_swx_pipeline *p)
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{
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struct thread *t = &p->threads[p->thread_id];
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struct instruction *ip = t->ip;
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TRACE("[Thread %2u] add (hh)\n", p->thread_id);
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/* Structs. */
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ALU_HH(t, ip, +);
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/* Thread. */
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thread_ip_inc(p);
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}
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static inline void
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instr_alu_add_mi_exec(struct rte_swx_pipeline *p)
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{
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struct thread *t = &p->threads[p->thread_id];
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struct instruction *ip = t->ip;
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TRACE("[Thread %2u] add (mi)\n", p->thread_id);
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/* Structs. */
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ALU_MI(t, ip, +);
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/* Thread. */
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thread_ip_inc(p);
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}
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static inline void
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instr_alu_add_hi_exec(struct rte_swx_pipeline *p)
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{
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struct thread *t = &p->threads[p->thread_id];
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struct instruction *ip = t->ip;
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TRACE("[Thread %2u] add (hi)\n", p->thread_id);
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/* Structs. */
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ALU_HI(t, ip, +);
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/* Thread. */
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thread_ip_inc(p);
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}
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#define RTE_SWX_INSTRUCTION_TOKENS_MAX 16
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static int
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@ -2820,6 +3107,14 @@ instr_translate(struct rte_swx_pipeline *p,
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instr,
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data);
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if (!strcmp(tokens[tpos], "add"))
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return instr_alu_add_translate(p,
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action,
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&tokens[tpos],
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n_tokens - tpos,
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instr,
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data);
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CHECK(0, EINVAL);
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}
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@ -2977,6 +3272,13 @@ static instr_exec_t instruction_table[] = {
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[INSTR_DMA_HT6] = instr_dma_ht6_exec,
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[INSTR_DMA_HT7] = instr_dma_ht7_exec,
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[INSTR_DMA_HT8] = instr_dma_ht8_exec,
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[INSTR_ALU_ADD] = instr_alu_add_exec,
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[INSTR_ALU_ADD_MH] = instr_alu_add_mh_exec,
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[INSTR_ALU_ADD_HM] = instr_alu_add_hm_exec,
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[INSTR_ALU_ADD_HH] = instr_alu_add_hh_exec,
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[INSTR_ALU_ADD_MI] = instr_alu_add_mi_exec,
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[INSTR_ALU_ADD_HI] = instr_alu_add_hi_exec,
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};
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static inline void
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