d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

net/ice: enable QinQ filter for switch

Browse Source 
Enable the double VLAN support for switch QinQ filtering.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
This commit is contained in:
Junfeng Guo 2021-01-18 14:07:41 +00:00 committed by Ferruh Yigit
parent bd49d1d343
commit bb3386f348
4 changed files with 113 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
doc/guides/rel_notes/release_21_02.rst
View File

@ -82,6 +82,10 @@ New Features
* Added support for 64B completion queue entries
* **Updated Intel ice driver.**
* Added Double VLAN support for DCF switch QinQ filtering.
* **Updated Mellanox mlx5 driver.**
Updated the Mellanox mlx5 driver with new features and improvements, including:

15
drivers/net/ice/ice_generic_flow.c
View File

@ -1455,6 +1455,14 @@ enum rte_flow_item_type pattern_eth_qinq_pppoes[] = {
RTE_FLOW_ITEM_TYPE_PPPOES,
RTE_FLOW_ITEM_TYPE_END,
};
enum rte_flow_item_type pattern_eth_qinq_pppoes_proto[] = {
RTE_FLOW_ITEM_TYPE_ETH,
RTE_FLOW_ITEM_TYPE_VLAN,
RTE_FLOW_ITEM_TYPE_VLAN,
RTE_FLOW_ITEM_TYPE_PPPOES,
RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID,
RTE_FLOW_ITEM_TYPE_END,
};
enum rte_flow_item_type pattern_eth_pppoes_ipv4[] = {
RTE_FLOW_ITEM_TYPE_ETH,
RTE_FLOW_ITEM_TYPE_PPPOES,
@ -2100,29 +2108,36 @@ static struct ice_ptype_match ice_ptype_map[] = {
{pattern_eth_ipv6_pfcp, ICE_MAC_IPV6_PFCP_SESSION},
{pattern_ethertype, ICE_PTYPE_MAC_PAY},
{pattern_ethertype_vlan, ICE_PTYPE_MAC_PAY},
{pattern_ethertype_qinq, ICE_PTYPE_MAC_PAY},
{pattern_eth_arp, ICE_PTYPE_MAC_PAY},
{pattern_eth_vlan_ipv4, ICE_PTYPE_IPV4_PAY},
{pattern_eth_qinq_ipv4, ICE_PTYPE_IPV4_PAY},
{pattern_eth_vlan_ipv4_udp, ICE_PTYPE_IPV4_UDP_PAY},
{pattern_eth_vlan_ipv4_tcp, ICE_PTYPE_IPV4_TCP_PAY},
{pattern_eth_vlan_ipv4_sctp, ICE_PTYPE_IPV4_SCTP_PAY},
{pattern_eth_vlan_ipv6, ICE_PTYPE_IPV6_PAY},
{pattern_eth_qinq_ipv6, ICE_PTYPE_IPV6_PAY},
{pattern_eth_vlan_ipv6_udp, ICE_PTYPE_IPV6_UDP_PAY},
{pattern_eth_vlan_ipv6_tcp, ICE_PTYPE_IPV6_TCP_PAY},
{pattern_eth_vlan_ipv6_sctp, ICE_PTYPE_IPV6_SCTP_PAY},
{pattern_eth_pppoes, ICE_MAC_PPPOE_PAY},
{pattern_eth_vlan_pppoes, ICE_MAC_PPPOE_PAY},
{pattern_eth_qinq_pppoes, ICE_MAC_PPPOE_PAY},
{pattern_eth_pppoes_proto, ICE_MAC_PPPOE_PAY},
{pattern_eth_vlan_pppoes_proto, ICE_MAC_PPPOE_PAY},
{pattern_eth_qinq_pppoes_proto, ICE_MAC_PPPOE_PAY},
{pattern_eth_pppoes_ipv4, ICE_MAC_PPPOE_IPV4_PAY},
{pattern_eth_pppoes_ipv4_udp, ICE_MAC_PPPOE_IPV4_UDP_PAY},
{pattern_eth_pppoes_ipv4_tcp, ICE_MAC_PPPOE_IPV4_TCP},
{pattern_eth_vlan_pppoes_ipv4, ICE_MAC_PPPOE_IPV4_PAY},
{pattern_eth_qinq_pppoes_ipv4, ICE_MAC_PPPOE_IPV4_PAY},
{pattern_eth_vlan_pppoes_ipv4_tcp, ICE_MAC_PPPOE_IPV4_TCP},
{pattern_eth_vlan_pppoes_ipv4_udp, ICE_MAC_PPPOE_IPV4_UDP_PAY},
{pattern_eth_pppoes_ipv6, ICE_MAC_PPPOE_IPV6_PAY},
{pattern_eth_pppoes_ipv6_udp, ICE_MAC_PPPOE_IPV6_UDP_PAY},
{pattern_eth_pppoes_ipv6_tcp, ICE_MAC_PPPOE_IPV6_TCP},
{pattern_eth_vlan_pppoes_ipv6, ICE_MAC_PPPOE_IPV6_PAY},
{pattern_eth_qinq_pppoes_ipv6, ICE_MAC_PPPOE_IPV6_PAY},
{pattern_eth_vlan_pppoes_ipv6_tcp, ICE_MAC_PPPOE_IPV6_TCP},
{pattern_eth_vlan_pppoes_ipv6_udp, ICE_MAC_PPPOE_IPV6_UDP_PAY},
{pattern_eth_ipv4_udp_vxlan_ipv4, ICE_MAC_IPV4_TUN_IPV4_PAY},

1
drivers/net/ice/ice_generic_flow.h
View File

@ -426,6 +426,7 @@ extern enum rte_flow_item_type pattern_eth_pppoes_proto[];
extern enum rte_flow_item_type pattern_eth_vlan_pppoes[];
extern enum rte_flow_item_type pattern_eth_vlan_pppoes_proto[];
extern enum rte_flow_item_type pattern_eth_qinq_pppoes[];
extern enum rte_flow_item_type pattern_eth_qinq_pppoes_proto[];
extern enum rte_flow_item_type pattern_eth_pppoes_ipv4[];
extern enum rte_flow_item_type pattern_eth_vlan_pppoes_ipv4[];
extern enum rte_flow_item_type pattern_eth_qinq_pppoes_ipv4[];

104
drivers/net/ice/ice_switch_filter.c
View File

@ -35,11 +35,15 @@
#define ICE_SW_INSET_ETHER ( \
ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE)
#define ICE_SW_INSET_MAC_VLAN ( \
ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE | \
ICE_INSET_VLAN_OUTER)
ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE | \
ICE_INSET_VLAN_INNER)
#define ICE_SW_INSET_MAC_QINQ ( \
ICE_SW_INSET_MAC_VLAN | ICE_INSET_VLAN_OUTER)
#define ICE_SW_INSET_MAC_IPV4 ( \
ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \
ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS)
#define ICE_SW_INSET_MAC_QINQ_IPV4 ( \
ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV4)
#define ICE_SW_INSET_MAC_IPV4_TCP ( \
ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \
ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | \
@ -52,6 +56,8 @@
ICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \
ICE_INSET_IPV6_TC | ICE_INSET_IPV6_HOP_LIMIT | \
ICE_INSET_IPV6_NEXT_HDR)
#define ICE_SW_INSET_MAC_QINQ_IPV6 ( \
ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV6)
#define ICE_SW_INSET_MAC_IPV6_TCP ( \
ICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \
ICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TC | \
@ -146,6 +152,8 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = {
ICE_SW_INSET_ETHER, ICE_INSET_NONE},
{pattern_ethertype_vlan,
ICE_SW_INSET_MAC_VLAN, ICE_INSET_NONE},
{pattern_ethertype_qinq,
ICE_SW_INSET_MAC_QINQ, ICE_INSET_NONE},
{pattern_eth_arp,
ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv4,
@ -226,6 +234,18 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = {
ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv6_pfcp,
ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv4,
ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE},
{pattern_eth_qinq_ipv6,
ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes,
ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_proto,
ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_ipv4,
ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_ipv6,
ICE_SW_INSET_MAC_PPPOE_IPV6, ICE_INSET_NONE},
};
static struct
@ -234,6 +254,8 @@ ice_pattern_match_item ice_switch_pattern_perm_list[] = {
ICE_SW_INSET_ETHER, ICE_INSET_NONE},
{pattern_ethertype_vlan,
ICE_SW_INSET_MAC_VLAN, ICE_INSET_NONE},
{pattern_ethertype_qinq,
ICE_SW_INSET_MAC_QINQ, ICE_INSET_NONE},
{pattern_eth_arp,
ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv4,
@ -314,6 +336,18 @@ ice_pattern_match_item ice_switch_pattern_perm_list[] = {
ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv6_pfcp,
ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv4,
ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE},
{pattern_eth_qinq_ipv6,
ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes,
ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_proto,
ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_ipv4,
ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_ipv6,
ICE_SW_INSET_MAC_PPPOE_IPV6, ICE_INSET_NONE},
};
static int
@ -446,6 +480,8 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],
bool pppoe_elem_valid = 0;
bool pppoe_patt_valid = 0;
bool pppoe_prot_valid = 0;
bool inner_vlan_valid = 0;
bool outer_vlan_valid = 0;
bool tunnel_valid = 0;
bool profile_rule = 0;
bool nvgre_valid = 0;
@ -992,23 +1028,40 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],
"Invalid VLAN item");
return 0;
}
if (!outer_vlan_valid &&
(*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||
*tun_type == ICE_NON_TUN_QINQ))
outer_vlan_valid = 1;
else if (!inner_vlan_valid &&
(*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||
*tun_type == ICE_NON_TUN_QINQ))
inner_vlan_valid = 1;
else if (!inner_vlan_valid)
inner_vlan_valid = 1;
if (vlan_spec && vlan_mask) {
list[t].type = ICE_VLAN_OFOS;
if (outer_vlan_valid && !inner_vlan_valid) {
list[t].type = ICE_VLAN_EX;
input_set |= ICE_INSET_VLAN_OUTER;
} else if (inner_vlan_valid) {
list[t].type = ICE_VLAN_OFOS;
input_set |= ICE_INSET_VLAN_INNER;
}
if (vlan_mask->tci) {
list[t].h_u.vlan_hdr.vlan =
vlan_spec->tci;
list[t].m_u.vlan_hdr.vlan =
vlan_mask->tci;
input_set |= ICE_INSET_VLAN_OUTER;
input_set_byte += 2;
}
if (vlan_mask->inner_type) {
list[t].h_u.vlan_hdr.type =
vlan_spec->inner_type;
list[t].m_u.vlan_hdr.type =
vlan_mask->inner_type;
input_set |= ICE_INSET_ETHERTYPE;
input_set_byte += 2;
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM,
item,
"Invalid VLAN input set.");
return 0;
}
t++;
}
@ -1310,8 +1363,27 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],
}
}
if (*tun_type == ICE_SW_TUN_PPPOE_PAY &&
inner_vlan_valid && outer_vlan_valid)
*tun_type = ICE_SW_TUN_PPPOE_PAY_QINQ;
else if (*tun_type == ICE_SW_TUN_PPPOE &&
inner_vlan_valid && outer_vlan_valid)
*tun_type = ICE_SW_TUN_PPPOE_QINQ;
else if (*tun_type == ICE_NON_TUN &&
inner_vlan_valid && outer_vlan_valid)
*tun_type = ICE_NON_TUN_QINQ;
else if (*tun_type == ICE_SW_TUN_AND_NON_TUN &&
inner_vlan_valid && outer_vlan_valid)
*tun_type = ICE_SW_TUN_AND_NON_TUN_QINQ;
if (pppoe_patt_valid && !pppoe_prot_valid) {
if (ipv6_valid && udp_valid)
if (inner_vlan_valid && outer_vlan_valid && ipv4_valid)
*tun_type = ICE_SW_TUN_PPPOE_IPV4_QINQ;
else if (inner_vlan_valid && outer_vlan_valid && ipv6_valid)
*tun_type = ICE_SW_TUN_PPPOE_IPV6_QINQ;
else if (inner_vlan_valid && outer_vlan_valid)
*tun_type = ICE_SW_TUN_PPPOE_QINQ;
else if (ipv6_valid && udp_valid)
*tun_type = ICE_SW_TUN_PPPOE_IPV6_UDP;
else if (ipv6_valid && tcp_valid)
*tun_type = ICE_SW_TUN_PPPOE_IPV6_TCP;
@ -1589,6 +1661,7 @@ ice_switch_parse_pattern_action(struct ice_adapter *ad,
uint16_t lkups_num = 0;
const struct rte_flow_item *item = pattern;
uint16_t item_num = 0;
uint16_t vlan_num = 0;
enum ice_sw_tunnel_type tun_type =
ICE_NON_TUN;
struct ice_pattern_match_item *pattern_match_item = NULL;
@ -1604,6 +1677,10 @@ ice_switch_parse_pattern_action(struct ice_adapter *ad,
if (eth_mask->type == UINT16_MAX)
tun_type = ICE_SW_TUN_AND_NON_TUN;
}
if (item->type == RTE_FLOW_ITEM_TYPE_VLAN)
vlan_num++;
/* reserve one more memory slot for ETH which may
* consume 2 lookup items.
*/
@ -1611,6 +1688,11 @@ ice_switch_parse_pattern_action(struct ice_adapter *ad,
item_num++;
}
if (vlan_num == 2 && tun_type == ICE_SW_TUN_AND_NON_TUN)
tun_type = ICE_SW_TUN_AND_NON_TUN_QINQ;
else if (vlan_num == 2)
tun_type = ICE_NON_TUN_QINQ;
list = rte_zmalloc(NULL, item_num * sizeof(*list), 0);
if (!list) {
rte_flow_error_set(error, EINVAL,