net/enetfec: support queue configuration
This patch adds Rx/Tx queue configuration setup operations. On packet reception the respective BD Ring status bit is set which is then used for packet processing. Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com> Signed-off-by: Apeksha Gupta <apeksha.gupta@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Apeksha Gupta
Ferruh Yigit
parent
b84fdd3963
commit
bb5b5bf1e5
@ -32,6 +32,11 @@
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#define NUM_OF_BD_QUEUES 6
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/* Supported Rx offloads */
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static uint64_t dev_rx_offloads_sup =
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RTE_ETH_RX_OFFLOAD_CHECKSUM |
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RTE_ETH_RX_OFFLOAD_VLAN;
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/*
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* This function is called to start or restart the ENETFEC during a link
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* change, transmit timeout, or to reconfigure the ENETFEC. The network
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@ -177,10 +182,223 @@ enetfec_eth_stop(struct rte_eth_dev *dev)
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return 0;
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}
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static int
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enetfec_eth_info(__rte_unused struct rte_eth_dev *dev,
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struct rte_eth_dev_info *dev_info)
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{
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dev_info->max_rx_pktlen = ENETFEC_MAX_RX_PKT_LEN;
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dev_info->max_rx_queues = ENETFEC_MAX_Q;
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dev_info->max_tx_queues = ENETFEC_MAX_Q;
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dev_info->rx_offload_capa = dev_rx_offloads_sup;
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return 0;
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}
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static const unsigned short offset_des_active_rxq[] = {
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ENETFEC_RDAR_0, ENETFEC_RDAR_1, ENETFEC_RDAR_2
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};
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static const unsigned short offset_des_active_txq[] = {
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ENETFEC_TDAR_0, ENETFEC_TDAR_1, ENETFEC_TDAR_2
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};
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static int
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enetfec_tx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id __rte_unused,
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const struct rte_eth_txconf *tx_conf)
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{
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struct enetfec_private *fep = dev->data->dev_private;
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unsigned int i;
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struct bufdesc *bdp, *bd_base;
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struct enetfec_priv_tx_q *txq;
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unsigned int size;
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unsigned int dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
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sizeof(struct bufdesc);
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unsigned int dsize_log2 = fls64(dsize);
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/* Tx deferred start is not supported */
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if (tx_conf->tx_deferred_start) {
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ENETFEC_PMD_ERR("Tx deferred start not supported");
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return -EINVAL;
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}
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/* allocate transmit queue */
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txq = rte_zmalloc(NULL, sizeof(*txq), RTE_CACHE_LINE_SIZE);
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if (txq == NULL) {
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ENETFEC_PMD_ERR("transmit queue allocation failed");
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return -ENOMEM;
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}
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if (nb_desc > MAX_TX_BD_RING_SIZE) {
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nb_desc = MAX_TX_BD_RING_SIZE;
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ENETFEC_PMD_WARN("modified the nb_desc to MAX_TX_BD_RING_SIZE");
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}
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txq->bd.ring_size = nb_desc;
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fep->total_tx_ring_size += txq->bd.ring_size;
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fep->tx_queues[queue_idx] = txq;
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rte_write32(rte_cpu_to_le_32(fep->bd_addr_p_t[queue_idx]),
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(uint8_t *)fep->hw_baseaddr_v + ENETFEC_TD_START(queue_idx));
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/* Set transmit descriptor base. */
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txq = fep->tx_queues[queue_idx];
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txq->fep = fep;
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size = dsize * txq->bd.ring_size;
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bd_base = (struct bufdesc *)fep->dma_baseaddr_t[queue_idx];
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txq->bd.queue_id = queue_idx;
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txq->bd.base = bd_base;
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txq->bd.cur = bd_base;
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txq->bd.d_size = dsize;
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txq->bd.d_size_log2 = dsize_log2;
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txq->bd.active_reg_desc = (uint8_t *)fep->hw_baseaddr_v +
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offset_des_active_txq[queue_idx];
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bd_base = (struct bufdesc *)(((uintptr_t)bd_base) + size);
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txq->bd.last = (struct bufdesc *)(((uintptr_t)bd_base) - dsize);
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bdp = txq->bd.base;
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bdp = txq->bd.cur;
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for (i = 0; i < txq->bd.ring_size; i++) {
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/* Initialize the BD for every fragment in the page. */
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rte_write16(rte_cpu_to_le_16(0), &bdp->bd_sc);
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if (txq->tx_mbuf[i] != NULL) {
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rte_pktmbuf_free(txq->tx_mbuf[i]);
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txq->tx_mbuf[i] = NULL;
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}
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rte_write32(0, &bdp->bd_bufaddr);
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bdp = enet_get_nextdesc(bdp, &txq->bd);
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}
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/* Set the last buffer to wrap */
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bdp = enet_get_prevdesc(bdp, &txq->bd);
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rte_write16((rte_cpu_to_le_16(TX_BD_WRAP) |
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rte_read16(&bdp->bd_sc)), &bdp->bd_sc);
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txq->dirty_tx = bdp;
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dev->data->tx_queues[queue_idx] = fep->tx_queues[queue_idx];
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return 0;
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}
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static int
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enetfec_rx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_rx_desc,
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unsigned int socket_id __rte_unused,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool)
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{
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struct enetfec_private *fep = dev->data->dev_private;
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unsigned int i;
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struct bufdesc *bd_base;
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struct bufdesc *bdp;
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struct enetfec_priv_rx_q *rxq;
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unsigned int size;
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unsigned int dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
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sizeof(struct bufdesc);
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unsigned int dsize_log2 = fls64(dsize);
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/* Rx deferred start is not supported */
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if (rx_conf->rx_deferred_start) {
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ENETFEC_PMD_ERR("Rx deferred start not supported");
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return -EINVAL;
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}
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/* allocate receive queue */
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rxq = rte_zmalloc(NULL, sizeof(*rxq), RTE_CACHE_LINE_SIZE);
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if (rxq == NULL) {
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ENETFEC_PMD_ERR("receive queue allocation failed");
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return -ENOMEM;
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}
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if (nb_rx_desc > MAX_RX_BD_RING_SIZE) {
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nb_rx_desc = MAX_RX_BD_RING_SIZE;
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ENETFEC_PMD_WARN("modified the nb_desc to MAX_RX_BD_RING_SIZE");
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}
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rxq->bd.ring_size = nb_rx_desc;
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fep->total_rx_ring_size += rxq->bd.ring_size;
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fep->rx_queues[queue_idx] = rxq;
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rte_write32(rte_cpu_to_le_32(fep->bd_addr_p_r[queue_idx]),
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(uint8_t *)fep->hw_baseaddr_v + ENETFEC_RD_START(queue_idx));
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rte_write32(rte_cpu_to_le_32(PKT_MAX_BUF_SIZE),
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(uint8_t *)fep->hw_baseaddr_v + ENETFEC_MRB_SIZE(queue_idx));
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/* Set receive descriptor base. */
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rxq = fep->rx_queues[queue_idx];
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rxq->pool = mb_pool;
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size = dsize * rxq->bd.ring_size;
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bd_base = (struct bufdesc *)fep->dma_baseaddr_r[queue_idx];
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rxq->bd.queue_id = queue_idx;
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rxq->bd.base = bd_base;
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rxq->bd.cur = bd_base;
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rxq->bd.d_size = dsize;
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rxq->bd.d_size_log2 = dsize_log2;
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rxq->bd.active_reg_desc = (uint8_t *)fep->hw_baseaddr_v +
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offset_des_active_rxq[queue_idx];
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bd_base = (struct bufdesc *)(((uintptr_t)bd_base) + size);
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rxq->bd.last = (struct bufdesc *)(((uintptr_t)bd_base) - dsize);
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rxq->fep = fep;
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bdp = rxq->bd.base;
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rxq->bd.cur = bdp;
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for (i = 0; i < nb_rx_desc; i++) {
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/* Initialize Rx buffers from pktmbuf pool */
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struct rte_mbuf *mbuf = rte_pktmbuf_alloc(mb_pool);
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if (mbuf == NULL) {
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ENETFEC_PMD_ERR("mbuf failed");
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goto err_alloc;
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}
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/* Get the virtual address & physical address */
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rte_write32(rte_cpu_to_le_32(rte_pktmbuf_iova(mbuf)),
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&bdp->bd_bufaddr);
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rxq->rx_mbuf[i] = mbuf;
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rte_write16(rte_cpu_to_le_16(RX_BD_EMPTY), &bdp->bd_sc);
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bdp = enet_get_nextdesc(bdp, &rxq->bd);
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}
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/* Initialize the receive buffer descriptors. */
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bdp = rxq->bd.cur;
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for (i = 0; i < rxq->bd.ring_size; i++) {
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/* Initialize the BD for every fragment in the page. */
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if (rte_read32(&bdp->bd_bufaddr) > 0)
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rte_write16(rte_cpu_to_le_16(RX_BD_EMPTY),
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&bdp->bd_sc);
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else
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rte_write16(rte_cpu_to_le_16(0), &bdp->bd_sc);
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bdp = enet_get_nextdesc(bdp, &rxq->bd);
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}
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/* Set the last buffer to wrap */
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bdp = enet_get_prevdesc(bdp, &rxq->bd);
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rte_write16((rte_cpu_to_le_16(RX_BD_WRAP) |
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rte_read16(&bdp->bd_sc)), &bdp->bd_sc);
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dev->data->rx_queues[queue_idx] = fep->rx_queues[queue_idx];
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rte_write32(0, fep->rx_queues[queue_idx]->bd.active_reg_desc);
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return 0;
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err_alloc:
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for (i = 0; i < nb_rx_desc; i++) {
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if (rxq->rx_mbuf[i] != NULL) {
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rte_pktmbuf_free(rxq->rx_mbuf[i]);
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rxq->rx_mbuf[i] = NULL;
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}
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}
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rte_free(rxq);
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return errno;
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}
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static const struct eth_dev_ops enetfec_ops = {
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.dev_configure = enetfec_eth_configure,
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.dev_start = enetfec_eth_start,
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.dev_stop = enetfec_eth_stop
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.dev_stop = enetfec_eth_stop,
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.dev_infos_get = enetfec_eth_info,
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.rx_queue_setup = enetfec_rx_queue_setup,
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.tx_queue_setup = enetfec_tx_queue_setup
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};
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static int
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@ -10,9 +10,13 @@
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/* full duplex */
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#define FULL_DUPLEX 0x00
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#define MAX_TX_BD_RING_SIZE 512 /* It should be power of 2 */
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#define MAX_RX_BD_RING_SIZE 512
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#define PKT_MAX_BUF_SIZE 1984
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#define OPT_FRAME_SIZE (PKT_MAX_BUF_SIZE << 16)
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#define ENETFEC_MAX_RX_PKT_LEN 3000
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#define __iomem
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/*
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* ENETFEC can support 1 rx and tx queue..
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*/
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@ -22,6 +26,49 @@
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#define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })
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#define readl(p) rte_read32(p)
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struct bufdesc {
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uint16_t bd_datlen; /* buffer data length */
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uint16_t bd_sc; /* buffer control & status */
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uint32_t bd_bufaddr; /* buffer address */
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};
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struct bufdesc_ex {
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struct bufdesc desc;
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uint32_t bd_esc;
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uint32_t bd_prot;
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uint32_t bd_bdu;
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uint32_t ts;
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uint16_t res0[4];
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};
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struct bufdesc_prop {
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int queue_id;
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/* Addresses of Tx and Rx buffers */
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struct bufdesc *base;
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struct bufdesc *last;
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struct bufdesc *cur;
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void __iomem *active_reg_desc;
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uint64_t descr_baseaddr_p;
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unsigned short ring_size;
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unsigned char d_size;
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unsigned char d_size_log2;
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};
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struct enetfec_priv_tx_q {
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struct bufdesc_prop bd;
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struct rte_mbuf *tx_mbuf[MAX_TX_BD_RING_SIZE];
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struct bufdesc *dirty_tx;
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struct rte_mempool *pool;
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struct enetfec_private *fep;
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};
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struct enetfec_priv_rx_q {
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struct bufdesc_prop bd;
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struct rte_mbuf *rx_mbuf[MAX_RX_BD_RING_SIZE];
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struct rte_mempool *pool;
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struct enetfec_private *fep;
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};
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struct enetfec_private {
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struct rte_eth_dev *dev;
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int full_duplex;
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@ -31,6 +78,8 @@ struct enetfec_private {
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uint32_t enetfec_e_cntl;
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uint16_t max_rx_queues;
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uint16_t max_tx_queues;
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unsigned int total_tx_ring_size;
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unsigned int total_rx_ring_size;
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unsigned int reg_size;
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unsigned int bd_size;
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bool bufdesc_ex;
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@ -44,6 +93,34 @@ struct enetfec_private {
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uint32_t bd_addr_p_t[ENETFEC_MAX_Q];
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void *dma_baseaddr_r[ENETFEC_MAX_Q];
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void *dma_baseaddr_t[ENETFEC_MAX_Q];
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struct enetfec_priv_rx_q *rx_queues[ENETFEC_MAX_Q];
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struct enetfec_priv_tx_q *tx_queues[ENETFEC_MAX_Q];
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};
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static inline struct
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bufdesc *enet_get_nextdesc(struct bufdesc *bdp, struct bufdesc_prop *bd)
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{
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return (bdp >= bd->last) ? bd->base
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: (struct bufdesc *)(((uintptr_t)bdp) + bd->d_size);
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}
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static inline int
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fls64(unsigned long word)
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{
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return (64 - __builtin_clzl(word)) - 1;
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}
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static inline struct
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bufdesc *enet_get_prevdesc(struct bufdesc *bdp, struct bufdesc_prop *bd)
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{
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return (bdp <= bd->base) ? bd->last
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: (struct bufdesc *)(((uintptr_t)bdp) - bd->d_size);
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}
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static inline int
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enet_get_bd_index(struct bufdesc *bdp, struct bufdesc_prop *bd)
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{
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return ((const char *)bdp - (const char *)bd->base) >> bd->d_size_log2;
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}
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#endif /*__ENETFEC_ETHDEV_H__*/
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