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bus/fslmc: support 32 enqueues/dequeues for LX2

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LX2 can support upto 32 frames in one hw pull request.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
This commit is contained in:
Nipun Gupta 2018-10-12 15:34:18 +05:30 committed by Thomas Monjalon
parent 293c0ca94c
commit bd23b1a827
7 changed files with 48 additions and 16 deletions
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17
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
View File

@ -53,6 +53,11 @@ static uint32_t io_space_count;
/* Variable to store DPAA2 platform type */
uint32_t dpaa2_svr_family;
/* Variable to store DPAA2 DQRR size */
uint8_t dpaa2_dqrr_size;
/* Variable to store DPAA2 EQCR size */
uint8_t dpaa2_eqcr_size;
/*Stashing Macros default for LS208x*/
static int dpaa2_core_cluster_base = 0x04;
static int dpaa2_cluster_sz = 2;
@ -125,7 +130,7 @@ static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
cpu_mask, token);
ret = system(command);
if (ret < 0)
DPAA2_BUS_WARN(
DPAA2_BUS_DEBUG(
"Failed to affine interrupts on respective core");
else
DPAA2_BUS_DEBUG(" %s command is executed", command);
@ -409,6 +414,14 @@ dpaa2_create_dpio_device(int vdev_fd,
DPAA2_BUS_DEBUG("LX2160 Platform Detected");
}
dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
if (dpaa2_svr_family == SVR_LX2160A) {
dpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE;
dpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE;
} else {
dpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE;
dpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE;
}
}
if (dpaa2_svr_family == SVR_LX2160A)
@ -492,7 +505,7 @@ dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
q_storage->dq_storage[i] = rte_malloc(NULL,
DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
dpaa2_dqrr_size * sizeof(struct qbman_result),
RTE_CACHE_LINE_SIZE);
if (!q_storage->dq_storage[i])
goto fail;

4
drivers/bus/fslmc/portal/dpaa2_hw_dpio.h
View File

@ -30,6 +30,10 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
/* Variable to store DPAA2 platform type */
extern uint32_t dpaa2_svr_family;
/* Variable to store DPAA2 DQRR size */
extern uint8_t dpaa2_dqrr_size;
/* Variable to store DPAA2 EQCR size */
extern uint8_t dpaa2_eqcr_size;
extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];

22
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
* Copyright 2016 NXP
* Copyright 2016-2018 NXP
*
*/
@ -32,11 +32,23 @@
#define VLAN_TAG_SIZE 4 /** < Vlan Header Length */
#endif
#define MAX_TX_RING_SLOTS 8
/** <Maximum number of slots available in TX ring*/
/* Maximum number of slots available in TX ring */
#define MAX_TX_RING_SLOTS 32
#define DPAA2_DQRR_RING_SIZE 16
/** <Maximum number of slots available in RX ring*/
/* Maximum number of slots available in RX ring */
#define DPAA2_EQCR_RING_SIZE 8
/* Maximum number of slots available in RX ring on LX2 */
#define DPAA2_LX2_EQCR_RING_SIZE 32
/* Maximum number of slots available in RX ring */
#define DPAA2_DQRR_RING_SIZE 16
/* Maximum number of slots available in RX ring on LX2 */
#define DPAA2_LX2_DQRR_RING_SIZE 32
/* EQCR shift to get EQCR size (2 >> 3) = 8 for LS2/LS2 */
#define DPAA2_EQCR_SHIFT 3
/* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */
#define DPAA2_LX2_EQCR_SHIFT 5
#define DPAA2_SWP_CENA_REGION 0
#define DPAA2_SWP_CINH_REGION 1

2
drivers/bus/fslmc/rte_bus_fslmc_version.map
View File

@ -121,6 +121,8 @@ DPDK_18.05 {
DPDK_18.11 {
global:
dpaa2_dqrr_size;
dpaa2_eqcr_size;
dpci_get_link_state;
dpci_get_opr;
dpci_get_peer_attributes;

7
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
View File

@ -1237,7 +1237,8 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
swp = DPAA2_PER_LCORE_PORTAL;
while (nb_ops) {
frames_to_send = (nb_ops >> 3) ? MAX_TX_RING_SLOTS : nb_ops;
frames_to_send = (nb_ops > dpaa2_eqcr_size) ?
dpaa2_eqcr_size : nb_ops;
for (loop = 0; loop < frames_to_send; loop++) {
/*Clear the unused FD fields before sending*/
@ -1396,8 +1397,8 @@ dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops,
qbman_pull_desc_clear(&pulldesc);
qbman_pull_desc_set_numframes(&pulldesc,
(nb_ops > DPAA2_DQRR_RING_SIZE) ?
DPAA2_DQRR_RING_SIZE : nb_ops);
(nb_ops > dpaa2_dqrr_size) ?
dpaa2_dqrr_size : nb_ops);
qbman_pull_desc_set_fq(&pulldesc, fqid);
qbman_pull_desc_set_storage(&pulldesc, dq_storage,
(dma_addr_t)DPAA2_VADDR_TO_IOVA(dq_storage),

4
drivers/event/dpaa2/dpaa2_eventdev.c
View File

@ -109,8 +109,8 @@ skip_linking:
evq_info = &dpaa2_portal->evq_info[queue_id];
while (nb_events) {
frames_to_send = (nb_events >> 3) ?
MAX_TX_RING_SLOTS : nb_events;
frames_to_send = (nb_events > dpaa2_eqcr_size) ?
dpaa2_eqcr_size : nb_events;
for (loop = 0; loop < frames_to_send; loop++) {
const struct rte_event *event = &ev[num_tx + loop];

8
drivers/net/dpaa2/dpaa2_rxtx.c
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
* Copyright 2016 NXP
* Copyright 2016-2018 NXP
*
*/
@ -476,8 +476,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
}
}
swp = DPAA2_PER_LCORE_ETHRX_PORTAL;
pull_size = (nb_pkts > DPAA2_DQRR_RING_SIZE) ?
DPAA2_DQRR_RING_SIZE : nb_pkts;
pull_size = (nb_pkts > dpaa2_dqrr_size) ? dpaa2_dqrr_size : nb_pkts;
if (unlikely(!q_storage->active_dqs)) {
q_storage->toggle = 0;
dq_storage = q_storage->dq_storage[q_storage->toggle];
@ -699,7 +698,8 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
goto skip_tx;
}
frames_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts;
frames_to_send = (nb_pkts > dpaa2_eqcr_size) ?
dpaa2_eqcr_size : nb_pkts;
for (loop = 0; loop < frames_to_send; loop++) {
if ((*bufs)->seqn) {