net/qede/base: add APIs for xcvr
Add API to query transceiver info and to retrieve link speed. Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
This commit is contained in:
Rasesh Mody
Ferruh Yigit
parent
803a4cf0e0
commit
bdc40630a8
@ -9,6 +9,7 @@
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#include "bcm_osal.h"
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#include "ecore.h"
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#include "ecore_status.h"
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#include "nvm_cfg.h"
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#include "ecore_mcp.h"
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#include "mcp_public.h"
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#include "reg_addr.h"
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@ -2130,19 +2131,20 @@ enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 *p_media_type)
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{
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enum _ecore_status_t rc = ECORE_SUCCESS;
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/* TODO - Add support for VFs */
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if (IS_VF(p_hwfn->p_dev))
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return ECORE_INVAL;
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if (!ecore_mcp_is_init(p_hwfn)) {
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DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
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DP_NOTICE(p_hwfn, false, "MFW is not initialized!\n");
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return ECORE_BUSY;
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}
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if (!p_ptt) {
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*p_media_type = MEDIA_UNSPECIFIED;
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return ECORE_INVAL;
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rc = ECORE_INVAL;
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} else {
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*p_media_type = ecore_rd(p_hwfn, p_ptt,
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p_hwfn->mcp_info->port_addr +
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@ -2153,6 +2155,197 @@ enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
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return ECORE_SUCCESS;
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}
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enum _ecore_status_t ecore_mcp_get_transceiver_data(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 *p_tranceiver_type)
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{
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enum _ecore_status_t rc = ECORE_SUCCESS;
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/* TODO - Add support for VFs */
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if (IS_VF(p_hwfn->p_dev))
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return ECORE_INVAL;
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if (!ecore_mcp_is_init(p_hwfn)) {
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DP_NOTICE(p_hwfn, false, "MFW is not initialized!\n");
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return ECORE_BUSY;
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}
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if (!p_ptt) {
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*p_tranceiver_type = ETH_TRANSCEIVER_TYPE_NONE;
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rc = ECORE_INVAL;
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} else {
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*p_tranceiver_type = ecore_rd(p_hwfn, p_ptt,
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p_hwfn->mcp_info->port_addr +
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offsetof(struct public_port,
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transceiver_data));
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}
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return rc;
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}
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static int is_transceiver_ready(u32 transceiver_state, u32 transceiver_type)
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{
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if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) &&
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((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) &&
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(transceiver_type != ETH_TRANSCEIVER_TYPE_NONE))
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return 1;
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return 0;
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}
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enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 *p_speed_mask)
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{
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u32 transceiver_data, transceiver_type, transceiver_state;
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ecore_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_data);
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transceiver_state = GET_MFW_FIELD(transceiver_data,
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ETH_TRANSCEIVER_STATE);
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transceiver_type = GET_MFW_FIELD(transceiver_data,
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ETH_TRANSCEIVER_TYPE);
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if (is_transceiver_ready(transceiver_state, transceiver_type) == 0)
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return ECORE_INVAL;
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switch (transceiver_type) {
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case ETH_TRANSCEIVER_TYPE_1G_LX:
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case ETH_TRANSCEIVER_TYPE_1G_SX:
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case ETH_TRANSCEIVER_TYPE_1G_PCC:
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case ETH_TRANSCEIVER_TYPE_1G_ACC:
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case ETH_TRANSCEIVER_TYPE_1000BASET:
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*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
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break;
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case ETH_TRANSCEIVER_TYPE_10G_SR:
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case ETH_TRANSCEIVER_TYPE_10G_LR:
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case ETH_TRANSCEIVER_TYPE_10G_LRM:
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case ETH_TRANSCEIVER_TYPE_10G_ER:
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case ETH_TRANSCEIVER_TYPE_10G_PCC:
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case ETH_TRANSCEIVER_TYPE_10G_ACC:
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case ETH_TRANSCEIVER_TYPE_4x10G:
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*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
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break;
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case ETH_TRANSCEIVER_TYPE_40G_LR4:
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case ETH_TRANSCEIVER_TYPE_40G_SR4:
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case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
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case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
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*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
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break;
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case ETH_TRANSCEIVER_TYPE_100G_AOC:
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case ETH_TRANSCEIVER_TYPE_100G_SR4:
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case ETH_TRANSCEIVER_TYPE_100G_LR4:
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case ETH_TRANSCEIVER_TYPE_100G_ER4:
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case ETH_TRANSCEIVER_TYPE_100G_ACC:
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*p_speed_mask =
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
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break;
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case ETH_TRANSCEIVER_TYPE_25G_SR:
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case ETH_TRANSCEIVER_TYPE_25G_LR:
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case ETH_TRANSCEIVER_TYPE_25G_AOC:
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case ETH_TRANSCEIVER_TYPE_25G_ACC_S:
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case ETH_TRANSCEIVER_TYPE_25G_ACC_M:
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case ETH_TRANSCEIVER_TYPE_25G_ACC_L:
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*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
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break;
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case ETH_TRANSCEIVER_TYPE_25G_CA_N:
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case ETH_TRANSCEIVER_TYPE_25G_CA_S:
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case ETH_TRANSCEIVER_TYPE_25G_CA_L:
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case ETH_TRANSCEIVER_TYPE_4x25G_CR:
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*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
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break;
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case ETH_TRANSCEIVER_TYPE_40G_CR4:
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case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR:
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*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
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break;
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case ETH_TRANSCEIVER_TYPE_100G_CR4:
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case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
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*p_speed_mask =
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
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break;
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case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
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case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
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case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC:
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*p_speed_mask =
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
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break;
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case ETH_TRANSCEIVER_TYPE_XLPPI:
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*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
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break;
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case ETH_TRANSCEIVER_TYPE_10G_BASET:
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*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
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break;
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default:
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DP_INFO(p_hwfn, "Unknown transcevier type 0x%x\n",
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transceiver_type);
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*p_speed_mask = 0xff;
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break;
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}
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return ECORE_SUCCESS;
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}
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enum _ecore_status_t ecore_mcp_get_board_config(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 *p_board_config)
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{
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u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr;
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enum _ecore_status_t rc = ECORE_SUCCESS;
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/* TODO - Add support for VFs */
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if (IS_VF(p_hwfn->p_dev))
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return ECORE_INVAL;
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if (!ecore_mcp_is_init(p_hwfn)) {
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DP_NOTICE(p_hwfn, false, "MFW is not initialized!\n");
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return ECORE_BUSY;
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}
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if (!p_ptt) {
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*p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED;
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rc = ECORE_INVAL;
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} else {
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nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt,
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MISC_REG_GEN_PURP_CR0);
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nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt,
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nvm_cfg_addr + 4);
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port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
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offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
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*p_board_config = ecore_rd(p_hwfn, p_ptt,
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port_cfg_addr +
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offsetof(struct nvm_cfg1_port,
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board_cfg));
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}
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return rc;
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}
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/* @DPDK */
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/* Old MFW has a global configuration for all PFs regarding RDMA support */
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static void
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@ -594,6 +594,52 @@ enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 *media_type);
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/**
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* @brief Get transceiver data of the port.
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*
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* @param p_dev - ecore dev pointer
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* @param p_ptt
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* @param p_transceiver_type - media type value
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*
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* @return enum _ecore_status_t -
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* ECORE_SUCCESS - Operation was successful.
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* ECORE_BUSY - Operation failed
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*/
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enum _ecore_status_t ecore_mcp_get_transceiver_data(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 *p_tranceiver_type);
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/**
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* @brief Get transceiver supported speed mask.
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*
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* @param p_dev - ecore dev pointer
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* @param p_ptt
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* @param p_speed_mask - Bit mask of all supported speeds.
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*
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* @return enum _ecore_status_t -
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* ECORE_SUCCESS - Operation was successful.
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* ECORE_BUSY - Operation failed
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*/
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enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 *p_speed_mask);
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/**
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* @brief Get board configuration.
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*
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* @param p_dev - ecore dev pointer
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* @param p_ptt
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* @param p_board_config - Board config.
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*
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* @return enum _ecore_status_t -
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* ECORE_SUCCESS - Operation was successful.
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* ECORE_BUSY - Operation failed
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*/
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enum _ecore_status_t ecore_mcp_get_board_config(struct ecore_hwfn *p_hwfn,
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struct ecore_ptt *p_ptt,
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u32 *p_board_config);
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/**
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* @brief - Sends a command to the MCP mailbox.
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*
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@ -800,6 +800,7 @@ struct public_port {
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#define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
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#define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
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#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
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#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
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