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net/bnxt: support tunnel offload

Browse Source 
Add support for tunnel offload APIs. Specifically the following
are supported.
tunnel_decap_set, tunnel_match, tunnel_action_decap_release,
tunnel_item_release.

This provides support for VXLAN decap action where two flows
can indicate tunnel offload rule. The first flow indicates the
tunnel properties and second flow indicates the inner packet
structure. The templates are updated to support this
feature.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
This commit is contained in:
Kishore Padmanabha 2021-09-20 13:12:07 +05:30 committed by Ajit Khaparde
parent ad9eed0248
commit bdf4a3c631
25 changed files with 13862 additions and 6763 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
devtools/parse-flow-support.sh
View File

@ -25,7 +25,8 @@ exclude() # <pattern>
$dir/tf_ulp/ulp_rte_handler_tbl.c |
grep -wo "$1[[:alnum:]_]*" | sort -u |
tr '\n' '|' | sed 's,.$,\n,')
grep -vE "$filter";;
exceptions='RTE_FLOW_ACTION_TYPE_SHARED'
grep -vE "$filter" | grep -vE $exceptions;;
*) cat
esac
}

4
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
View File

@ -37,9 +37,7 @@
enum bnxt_tf_rc {
BNXT_TF_RC_PARSE_ERR = -2,
BNXT_TF_RC_ERROR = -1,
BNXT_TF_RC_SUCCESS = 0,
BNXT_TF_RC_NORMAL = 1,
BNXT_TF_RC_FID = 2,
BNXT_TF_RC_SUCCESS = 0
};
/* eth IPv4 Type */

12
drivers/net/bnxt/tf_ulp/bnxt_ulp.c
View File

@ -860,8 +860,6 @@ ulp_ctx_init(struct bnxt *bp,
if (rc)
goto error_deinit;
ulp_tun_tbl_init(ulp_data->tun_tbl);
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
return rc;
@ -2064,3 +2062,13 @@ bnxt_ulp_cntxt_entry_release(void)
{
rte_spinlock_unlock(&bnxt_ulp_ctxt_lock);
}
/* Function to get the app tunnel details from the ulp context. */
struct bnxt_flow_app_tun_ent *
bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
{
if (!ulp || !ulp->cfg_data)
return NULL;
return ulp->cfg_data->app_tun;
}

20
drivers/net/bnxt/tf_ulp/bnxt_ulp.h
View File

@ -47,6 +47,18 @@ enum bnxt_ulp_flow_mem_type {
BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
};
enum bnxt_rte_flow_item_type {
BNXT_RTE_FLOW_ITEM_TYPE_END = (uint32_t)INT_MIN,
BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP,
BNXT_RTE_FLOW_ITEM_TYPE_LAST
};
enum bnxt_rte_flow_action_type {
BNXT_RTE_FLOW_ACTION_TYPE_END = (uint32_t)INT_MIN,
BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP,
BNXT_RTE_FLOW_ACTION_TYPE_LAST
};
struct bnxt_ulp_df_rule_info {
uint32_t def_port_flow_id;
uint8_t valid;
@ -79,6 +91,7 @@ struct bnxt_ulp_data {
bool accum_stats;
uint8_t app_id;
uint8_t num_shared_clients;
struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
};
struct bnxt_ulp_context {
@ -258,9 +271,6 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
void
bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
int32_t
ulp_post_process_tun_flow(struct ulp_rte_parser_params *params);
struct bnxt_ulp_glb_resource_info *
bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);
@ -301,4 +311,8 @@ bnxt_ulp_cntxt_entry_release(void);
uint8_t
bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
struct bnxt_flow_app_tun_ent *
bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
#endif /* _BNXT_ULP_H_ */

212
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
View File

@ -12,6 +12,7 @@
#include "ulp_fc_mgr.h"
#include "ulp_port_db.h"
#include "ulp_ha_mgr.h"
#include "ulp_tun.h"
#include <rte_malloc.h>
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#include "ulp_template_debug_proto.h"
@ -101,12 +102,13 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
mapper_cparms->act_prop = &params->act_prop;
mapper_cparms->flow_id = params->fid;
mapper_cparms->parent_flow = params->parent_flow;
mapper_cparms->parent_fid = params->parent_fid;
mapper_cparms->child_flow = params->child_flow;
mapper_cparms->fld_bitmap = &params->fld_bitmap;
mapper_cparms->flow_pattern_id = params->flow_pattern_id;
mapper_cparms->act_pattern_id = params->act_pattern_id;
mapper_cparms->app_id = params->app_id;
mapper_cparms->port_id = params->port_id;
mapper_cparms->tun_idx = params->tun_idx;
/* update the signature fields into the computed field list */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,
@ -218,12 +220,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
params.func_id = func_id;
params.priority = attr->priority;
params.port_id = dev->data->port_id;
/* Perform the rte flow post process */
ret = bnxt_ulp_rte_parser_post_process(&params);
bnxt_ulp_rte_parser_post_process(&params);
/* do the tunnel offload process if any */
ret = ulp_tunnel_offload_process(&params);
if (ret == BNXT_TF_RC_ERROR)
goto free_fid;
else if (ret == BNXT_TF_RC_FID)
goto return_fid;
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
@ -249,7 +253,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
if (ret)
goto free_fid;
return_fid:
bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
flow_id = (struct rte_flow *)((uintptr_t)fid);
@ -314,11 +317,12 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
goto parse_error;
/* Perform the rte flow post process */
ret = bnxt_ulp_rte_parser_post_process(&params);
bnxt_ulp_rte_parser_post_process(&params);
/* do the tunnel offload process if any */
ret = ulp_tunnel_offload_process(&params);
if (ret == BNXT_TF_RC_ERROR)
goto parse_error;
else if (ret == BNXT_TF_RC_FID)
return 0;
ret = ulp_matcher_pattern_match(&params, &class_id);
@ -475,11 +479,201 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev,
return rc;
}
/* Tunnel offload Apis */
#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1
static int
bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev,
struct rte_flow_tunnel *tunnel,
struct rte_flow_action **pmd_actions,
uint32_t *num_of_actions,
struct rte_flow_error *error)
{
struct bnxt_ulp_context *ulp_ctx;
struct bnxt_flow_app_tun_ent *tun_entry;
int32_t rc = 0;
ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
if (ulp_ctx == NULL) {
BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
"ULP context uninitialized");
return -EINVAL;
}
if (tunnel == NULL) {
BNXT_TF_DBG(ERR, "No tunnel specified\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ATTR, NULL,
"no tunnel specified");
return -EINVAL;
}
if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ATTR, NULL,
"tunnel type unsupported");
return -EINVAL;
}
rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
if (rc < 0) {
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ATTR, NULL,
"tunnel decap set failed");
return -EINVAL;
}
rc = ulp_app_tun_entry_set_decap_action(tun_entry);
if (rc < 0) {
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ATTR, NULL,
"tunnel decap set failed");
return -EINVAL;
}
*pmd_actions = &tun_entry->action;
*num_of_actions = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
return 0;
}
static int
bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev,
struct rte_flow_tunnel *tunnel,
struct rte_flow_item **pmd_items,
uint32_t *num_of_items,
struct rte_flow_error *error)
{
struct bnxt_ulp_context *ulp_ctx;
struct bnxt_flow_app_tun_ent *tun_entry;
int32_t rc = 0;
ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
if (ulp_ctx == NULL) {
BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
"ULP context uninitialized");
return -EINVAL;
}
if (tunnel == NULL) {
BNXT_TF_DBG(ERR, "No tunnel specified\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
"no tunnel specified");
return -EINVAL;
}
if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) {
BNXT_TF_DBG(ERR, "Tunnel type unsupported\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
"tunnel type unsupported");
return -EINVAL;
}
rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry);
if (rc < 0) {
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ATTR, NULL,
"tunnel match set failed");
return -EINVAL;
}
rc = ulp_app_tun_entry_set_decap_item(tun_entry);
if (rc < 0) {
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ATTR, NULL,
"tunnel match set failed");
return -EINVAL;
}
*pmd_items = &tun_entry->item;
*num_of_items = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS;
return 0;
}
static int
bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev,
struct rte_flow_action *pmd_actions,
uint32_t num_actions,
struct rte_flow_error *error)
{
struct bnxt_ulp_context *ulp_ctx;
struct bnxt_flow_app_tun_ent *tun_entry;
const struct rte_flow_action *action_item = pmd_actions;
ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
if (ulp_ctx == NULL) {
BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
"ULP context uninitialized");
return -EINVAL;
}
if (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
BNXT_TF_DBG(ERR, "num actions is invalid\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ATTR, NULL,
"num actions is invalid");
return -EINVAL;
}
while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
if (action_item->type == (typeof(tun_entry->action.type))
BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP) {
tun_entry = ulp_app_tun_match_entry(ulp_ctx,
action_item->conf);
ulp_app_tun_entry_delete(tun_entry);
}
action_item++;
}
return 0;
}
static int
bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev,
struct rte_flow_item *pmd_items,
uint32_t num_items,
struct rte_flow_error *error)
{
struct bnxt_ulp_context *ulp_ctx;
struct bnxt_flow_app_tun_ent *tun_entry;
ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
if (ulp_ctx == NULL) {
BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
"ULP context uninitialized");
return -EINVAL;
}
if (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) {
BNXT_TF_DBG(ERR, "num items is invalid\n");
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ATTR, NULL,
"num items is invalid");
return -EINVAL;
}
tun_entry = ulp_app_tun_match_entry(ulp_ctx, pmd_items->spec);
ulp_app_tun_entry_delete(tun_entry);
return 0;
}
const struct rte_flow_ops bnxt_ulp_rte_flow_ops = {
.validate = bnxt_ulp_flow_validate,
.create = bnxt_ulp_flow_create,
.destroy = bnxt_ulp_flow_destroy,
.flush = bnxt_ulp_flow_flush,
.query = bnxt_ulp_flow_query,
.isolate = NULL
.isolate = NULL,
/* Tunnel offload callbacks */
.tunnel_decap_set = bnxt_ulp_tunnel_decap_set,
.tunnel_match = bnxt_ulp_tunnel_match,
.tunnel_action_decap_release = bnxt_ulp_tunnel_decap_release,
.tunnel_item_release = bnxt_ulp_tunnel_item_release,
.get_restore_info = NULL
};

2
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Wed Mar 17 11:31:19 2021 */
/* date: Mon May 17 15:30:41 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"

13925
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
View File

File diff suppressed because it is too large Load Diff

210
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Thu May 13 18:15:56 2021 */
/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@ -11,13 +11,13 @@
#define BNXT_ULP_REGFILE_MAX_SZ 40
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_GEN_TBL_MAX_SZ 10
#define BNXT_ULP_GEN_TBL_MAX_SZ 12
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768
#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687
#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849
#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
#define BNXT_ULP_CLASS_HID_SHFTR 23
#define BNXT_ULP_CLASS_HID_SHFTL 23
#define BNXT_ULP_CLASS_HID_SHFTR 24
#define BNXT_ULP_CLASS_HID_SHFTL 24
#define BNXT_ULP_CLASS_HID_MASK 32767
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
@ -36,14 +36,14 @@
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
#define BNXT_ULP_HDR_SIG_ID_SHIFT 4
#define BNXT_ULP_APP_ID_SHIFT 4
#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595
#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5
#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74
#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495
#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5
#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643
#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6
#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
#define ULP_THOR_CLASS_TBL_LIST_SIZE 33
#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242
#define ULP_THOR_CLASS_IDENT_LIST_SIZE 8
@ -113,7 +113,8 @@ enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000,
BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000,
BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000,
BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000
BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000,
BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000
};
enum bnxt_ulp_accept_opc {
@ -199,8 +200,10 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
BNXT_ULP_CF_IDX_WC_MATCH = 61,
BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
BNXT_ULP_CF_IDX_F1_DMAC = 63,
BNXT_ULP_CF_IDX_LAST = 64
BNXT_ULP_CF_IDX_TUNNEL_ID = 63,
BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64,
BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65,
BNXT_ULP_CF_IDX_LAST = 66
};
enum bnxt_ulp_cond_list_opc {
@ -315,7 +318,8 @@ enum bnxt_ulp_func_opc {
BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7,
BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8,
BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9,
BNXT_ULP_FUNC_OPC_LAST = 10
BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10,
BNXT_ULP_FUNC_OPC_LAST = 11
};
enum bnxt_ulp_func_src {
@ -497,7 +501,8 @@ enum bnxt_ulp_tcam_tbl_opc {
BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2,
BNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3,
BNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4,
BNXT_ULP_TCAM_TBL_OPC_LAST = 5
BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT = 5,
BNXT_ULP_TCAM_TBL_OPC_LAST = 6
};
enum bnxt_ulp_template_type {
@ -549,7 +554,8 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5
};
enum bnxt_ulp_act_prop_sz {
@ -1443,6 +1449,168 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_15db = 0x15db,
BNXT_ULP_CLASS_HID_1151 = 0x1151,
BNXT_ULP_CLASS_HID_315d = 0x315d,
BNXT_ULP_CLASS_HID_3612 = 0x3612,
BNXT_ULP_CLASS_HID_66da = 0x66da,
BNXT_ULP_CLASS_HID_6165 = 0x6165,
BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1,
BNXT_ULP_CLASS_HID_09cd = 0x09cd,
BNXT_ULP_CLASS_HID_3845 = 0x3845,
BNXT_ULP_CLASS_HID_11e9 = 0x11e9,
BNXT_ULP_CLASS_HID_4361 = 0x4361,
BNXT_ULP_CLASS_HID_218d = 0x218d,
BNXT_ULP_CLASS_HID_5105 = 0x5105,
BNXT_ULP_CLASS_HID_0c89 = 0x0c89,
BNXT_ULP_CLASS_HID_3e81 = 0x3e81,
BNXT_ULP_CLASS_HID_1dad = 0x1dad,
BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5,
BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
BNXT_ULP_CLASS_HID_57c1 = 0x57c1,
BNXT_ULP_CLASS_HID_33ed = 0x33ed,
BNXT_ULP_CLASS_HID_65e5 = 0x65e5,
BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9,
BNXT_ULP_CLASS_HID_261d = 0x261d,
BNXT_ULP_CLASS_HID_0571 = 0x0571,
BNXT_ULP_CLASS_HID_34f9 = 0x34f9,
BNXT_ULP_CLASS_HID_1d55 = 0x1d55,
BNXT_ULP_CLASS_HID_4fdd = 0x4fdd,
BNXT_ULP_CLASS_HID_2d31 = 0x2d31,
BNXT_ULP_CLASS_HID_5db9 = 0x5db9,
BNXT_ULP_CLASS_HID_0035 = 0x0035,
BNXT_ULP_CLASS_HID_323d = 0x323d,
BNXT_ULP_CLASS_HID_1111 = 0x1111,
BNXT_ULP_CLASS_HID_4019 = 0x4019,
BNXT_ULP_CLASS_HID_2975 = 0x2975,
BNXT_ULP_CLASS_HID_5b7d = 0x5b7d,
BNXT_ULP_CLASS_HID_3f51 = 0x3f51,
BNXT_ULP_CLASS_HID_6959 = 0x6959,
BNXT_ULP_CLASS_HID_0e85 = 0x0e85,
BNXT_ULP_CLASS_HID_380d = 0x380d,
BNXT_ULP_CLASS_HID_1f21 = 0x1f21,
BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9,
BNXT_ULP_CLASS_HID_1705 = 0x1705,
BNXT_ULP_CLASS_HID_418d = 0x418d,
BNXT_ULP_CLASS_HID_2721 = 0x2721,
BNXT_ULP_CLASS_HID_57a9 = 0x57a9,
BNXT_ULP_CLASS_HID_1a25 = 0x1a25,
BNXT_ULP_CLASS_HID_342d = 0x342d,
BNXT_ULP_CLASS_HID_2b01 = 0x2b01,
BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
BNXT_ULP_CLASS_HID_2325 = 0x2325,
BNXT_ULP_CLASS_HID_5d2d = 0x5d2d,
BNXT_ULP_CLASS_HID_3101 = 0x3101,
BNXT_ULP_CLASS_HID_6309 = 0x6309,
BNXT_ULP_CLASS_HID_0bad = 0x0bad,
BNXT_ULP_CLASS_HID_2535 = 0x2535,
BNXT_ULP_CLASS_HID_1869 = 0x1869,
BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1,
BNXT_ULP_CLASS_HID_136d = 0x136d,
BNXT_ULP_CLASS_HID_43f5 = 0x43f5,
BNXT_ULP_CLASS_HID_2129 = 0x2129,
BNXT_ULP_CLASS_HID_53b1 = 0x53b1,
BNXT_ULP_CLASS_HID_072d = 0x072d,
BNXT_ULP_CLASS_HID_3135 = 0x3135,
BNXT_ULP_CLASS_HID_1429 = 0x1429,
BNXT_ULP_CLASS_HID_4731 = 0x4731,
BNXT_ULP_CLASS_HID_2f6d = 0x2f6d,
BNXT_ULP_CLASS_HID_5f75 = 0x5f75,
BNXT_ULP_CLASS_HID_3d69 = 0x3d69,
BNXT_ULP_CLASS_HID_6f71 = 0x6f71,
BNXT_ULP_CLASS_HID_0dbd = 0x0dbd,
BNXT_ULP_CLASS_HID_3f25 = 0x3f25,
BNXT_ULP_CLASS_HID_1239 = 0x1239,
BNXT_ULP_CLASS_HID_4da1 = 0x4da1,
BNXT_ULP_CLASS_HID_153d = 0x153d,
BNXT_ULP_CLASS_HID_45a5 = 0x45a5,
BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9,
BNXT_ULP_CLASS_HID_55a1 = 0x55a1,
BNXT_ULP_CLASS_HID_193d = 0x193d,
BNXT_ULP_CLASS_HID_4b25 = 0x4b25,
BNXT_ULP_CLASS_HID_2e39 = 0x2e39,
BNXT_ULP_CLASS_HID_5921 = 0x5921,
BNXT_ULP_CLASS_HID_213d = 0x213d,
BNXT_ULP_CLASS_HID_5125 = 0x5125,
BNXT_ULP_CLASS_HID_3739 = 0x3739,
BNXT_ULP_CLASS_HID_093d = 0x093d,
BNXT_ULP_CLASS_HID_684d = 0x684d,
BNXT_ULP_CLASS_HID_2389 = 0x2389,
BNXT_ULP_CLASS_HID_00e5 = 0x00e5,
BNXT_ULP_CLASS_HID_316d = 0x316d,
BNXT_ULP_CLASS_HID_18c1 = 0x18c1,
BNXT_ULP_CLASS_HID_4a49 = 0x4a49,
BNXT_ULP_CLASS_HID_28a5 = 0x28a5,
BNXT_ULP_CLASS_HID_582d = 0x582d,
BNXT_ULP_CLASS_HID_05a1 = 0x05a1,
BNXT_ULP_CLASS_HID_37a9 = 0x37a9,
BNXT_ULP_CLASS_HID_1485 = 0x1485,
BNXT_ULP_CLASS_HID_458d = 0x458d,
BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1,
BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9,
BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5,
BNXT_ULP_CLASS_HID_6ccd = 0x6ccd,
BNXT_ULP_CLASS_HID_0b11 = 0x0b11,
BNXT_ULP_CLASS_HID_3d99 = 0x3d99,
BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5,
BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
BNXT_ULP_CLASS_HID_1291 = 0x1291,
BNXT_ULP_CLASS_HID_4419 = 0x4419,
BNXT_ULP_CLASS_HID_22b5 = 0x22b5,
BNXT_ULP_CLASS_HID_523d = 0x523d,
BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
BNXT_ULP_CLASS_HID_31b9 = 0x31b9,
BNXT_ULP_CLASS_HID_2e95 = 0x2e95,
BNXT_ULP_CLASS_HID_5f9d = 0x5f9d,
BNXT_ULP_CLASS_HID_26b1 = 0x26b1,
BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
BNXT_ULP_CLASS_HID_3495 = 0x3495,
BNXT_ULP_CLASS_HID_669d = 0x669d,
BNXT_ULP_CLASS_HID_0e39 = 0x0e39,
BNXT_ULP_CLASS_HID_20a1 = 0x20a1,
BNXT_ULP_CLASS_HID_1dfd = 0x1dfd,
BNXT_ULP_CLASS_HID_4e65 = 0x4e65,
BNXT_ULP_CLASS_HID_16f9 = 0x16f9,
BNXT_ULP_CLASS_HID_4661 = 0x4661,
BNXT_ULP_CLASS_HID_24bd = 0x24bd,
BNXT_ULP_CLASS_HID_5625 = 0x5625,
BNXT_ULP_CLASS_HID_02b9 = 0x02b9,
BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
BNXT_ULP_CLASS_HID_11bd = 0x11bd,
BNXT_ULP_CLASS_HID_42a5 = 0x42a5,
BNXT_ULP_CLASS_HID_2af9 = 0x2af9,
BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1,
BNXT_ULP_CLASS_HID_38fd = 0x38fd,
BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5,
BNXT_ULP_CLASS_HID_0829 = 0x0829,
BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1,
BNXT_ULP_CLASS_HID_17ad = 0x17ad,
BNXT_ULP_CLASS_HID_4835 = 0x4835,
BNXT_ULP_CLASS_HID_10a9 = 0x10a9,
BNXT_ULP_CLASS_HID_4031 = 0x4031,
BNXT_ULP_CLASS_HID_3e2d = 0x3e2d,
BNXT_ULP_CLASS_HID_5035 = 0x5035,
BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9,
BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
BNXT_ULP_CLASS_HID_2bad = 0x2bad,
BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5,
BNXT_ULP_CLASS_HID_24a9 = 0x24a9,
BNXT_ULP_CLASS_HID_54b1 = 0x54b1,
BNXT_ULP_CLASS_HID_32ad = 0x32ad,
BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9,
BNXT_ULP_CLASS_HID_7f35 = 0x7f35,
BNXT_ULP_CLASS_HID_34f1 = 0x34f1,
BNXT_ULP_CLASS_HID_179d = 0x179d,
BNXT_ULP_CLASS_HID_2615 = 0x2615,
BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9,
BNXT_ULP_CLASS_HID_5d31 = 0x5d31,
BNXT_ULP_CLASS_HID_3fdd = 0x3fdd,
BNXT_ULP_CLASS_HID_4f55 = 0x4f55,
BNXT_ULP_CLASS_HID_12d9 = 0x12d9,
BNXT_ULP_CLASS_HID_20d1 = 0x20d1,
BNXT_ULP_CLASS_HID_03fd = 0x03fd,
BNXT_ULP_CLASS_HID_52f5 = 0x52f5,
BNXT_ULP_CLASS_HID_3b99 = 0x3b99,
BNXT_ULP_CLASS_HID_4991 = 0x4991,
BNXT_ULP_CLASS_HID_2dbd = 0x2dbd,
BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5,
BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
@ -1876,8 +2044,8 @@ enum bnxt_ulp_act_hid {
};
enum bnxt_ulp_df_tpl {
BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3,
BNXT_ULP_DF_TPL_DEFAULT_VFR = 4
BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4,
BNXT_ULP_DF_TPL_DEFAULT_VFR = 5
};
#endif

654
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Wed Mar 17 11:31:19 2021 */
/* date: Thu May 20 11:56:39 2021 */
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
@ -415,272 +415,460 @@ enum bnxt_ulp_hf_0_2_0_bitmask {
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000,
BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
};
enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000,
BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x2000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x1000000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0800000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0100000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP = 0x0000040000000000
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
enum bnxt_ulp_hf_0_2_5_bitmask {
BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP = 0x0000010000000000
enum bnxt_ulp_hf_0_3_0_bitmask {
BNXT_ULP_HF_0_3_0_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
};
enum bnxt_ulp_hf_0_2_6_bitmask {
BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
enum bnxt_ulp_hf_0_3_1_bitmask {
BNXT_ULP_HF_0_3_1_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
};
enum bnxt_ulp_hf_0_2_7_bitmask {
BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
enum bnxt_ulp_hf_0_3_2_bitmask {
BNXT_ULP_HF_0_3_2_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
};
enum bnxt_ulp_hf_0_2_8_bitmask {
BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP = 0x0000008000000000
enum bnxt_ulp_hf_0_3_3_bitmask {
BNXT_ULP_HF_0_3_3_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
};
enum bnxt_ulp_hf_0_2_9_bitmask {
BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP = 0x0000002000000000
enum bnxt_ulp_hf_0_3_4_bitmask {
BNXT_ULP_HF_0_3_4_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_CSUM = 0x0000080000000000,
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_URP = 0x0000040000000000
};
enum bnxt_ulp_hf_0_2_10_bitmask {
BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
enum bnxt_ulp_hf_0_3_5_bitmask {
BNXT_ULP_HF_0_3_5_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_URP = 0x0000010000000000
};
enum bnxt_ulp_hf_0_2_11_bitmask {
BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
enum bnxt_ulp_hf_0_3_6_bitmask {
BNXT_ULP_HF_0_3_6_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
};
enum bnxt_ulp_hf_0_3_7_bitmask {
BNXT_ULP_HF_0_3_7_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
};
enum bnxt_ulp_hf_0_3_8_bitmask {
BNXT_ULP_HF_0_3_8_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_URP = 0x0000008000000000
};
enum bnxt_ulp_hf_0_3_9_bitmask {
BNXT_ULP_HF_0_3_9_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_URP = 0x0000002000000000
};
enum bnxt_ulp_hf_0_3_10_bitmask {
BNXT_ULP_HF_0_3_10_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
};
enum bnxt_ulp_hf_0_3_11_bitmask {
BNXT_ULP_HF_0_3_11_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
};
#endif

645
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Thu May 13 18:15:56 2021 */
/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@ -111,6 +111,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
},
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
BNXT_ULP_DIRECTION_INGRESS] = {
.name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE",
.result_num_entries = 256,
.result_num_bytes = 7,
.key_num_bytes = 2,
.num_buckets = 8,
.hash_tbl_entries = 1024,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
},
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 |
BNXT_ULP_DIRECTION_EGRESS] = {
.name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE",
.result_num_entries = 256,
.result_num_bytes = 7,
.key_num_bytes = 2,
.num_buckets = 8,
.hash_tbl_entries = 1024,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@ -3098,238 +3118,411 @@ uint8_t ulp_glb_field_tbl[] = {
[4098] = 2,
[4100] = 3,
[4102] = 4,
[4136] = 5,
[4138] = 6,
[4140] = 7,
[4142] = 8,
[4144] = 9,
[4146] = 10,
[4148] = 11,
[4150] = 12,
[4116] = 5,
[4118] = 6,
[4120] = 7,
[4122] = 8,
[4124] = 9,
[4126] = 10,
[4128] = 11,
[4130] = 12,
[4132] = 13,
[4134] = 14,
[4170] = 15,
[4172] = 16,
[4174] = 17,
[4176] = 18,
[4190] = 19,
[4191] = 20,
[4192] = 21,
[4193] = 22,
[4224] = 0,
[4225] = 1,
[4226] = 2,
[4228] = 3,
[4230] = 4,
[4244] = 5,
[4246] = 6,
[4248] = 7,
[4250] = 8,
[4252] = 9,
[4254] = 10,
[4256] = 11,
[4258] = 12,
[4260] = 13,
[4262] = 14,
[4227] = 20,
[4229] = 21,
[4231] = 22,
[4244] = 2,
[4245] = 23,
[4246] = 3,
[4247] = 24,
[4248] = 4,
[4249] = 25,
[4250] = 5,
[4251] = 26,
[4252] = 6,
[4253] = 27,
[4254] = 7,
[4255] = 28,
[4256] = 8,
[4257] = 29,
[4258] = 9,
[4259] = 30,
[4260] = 10,
[4261] = 31,
[4262] = 11,
[4263] = 32,
[4298] = 12,
[4300] = 13,
[4302] = 14,
[4304] = 15,
[4318] = 16,
[4319] = 17,
[4320] = 18,
[4321] = 19,
[4352] = 0,
[4353] = 1,
[4354] = 2,
[4356] = 3,
[4358] = 4,
[4392] = 8,
[4394] = 9,
[4396] = 10,
[4398] = 11,
[4400] = 12,
[4402] = 13,
[4404] = 14,
[4406] = 15,
[4434] = 5,
[4438] = 6,
[4442] = 7,
[4355] = 20,
[4357] = 21,
[4359] = 22,
[4372] = 2,
[4373] = 23,
[4374] = 3,
[4375] = 24,
[4376] = 4,
[4377] = 25,
[4378] = 5,
[4379] = 26,
[4380] = 6,
[4381] = 27,
[4382] = 7,
[4383] = 28,
[4384] = 8,
[4385] = 29,
[4386] = 9,
[4387] = 30,
[4388] = 10,
[4389] = 31,
[4390] = 11,
[4391] = 32,
[4409] = 33,
[4411] = 34,
[4413] = 35,
[4415] = 36,
[4417] = 37,
[4419] = 38,
[4421] = 39,
[4423] = 40,
[4425] = 41,
[4426] = 12,
[4428] = 13,
[4430] = 14,
[4432] = 15,
[4446] = 16,
[4447] = 17,
[4448] = 18,
[4449] = 19,
[4480] = 0,
[4481] = 1,
[4482] = 2,
[4484] = 3,
[4486] = 4,
[4500] = 8,
[4502] = 9,
[4504] = 10,
[4506] = 11,
[4508] = 12,
[4510] = 13,
[4512] = 14,
[4514] = 15,
[4516] = 16,
[4518] = 17,
[4562] = 5,
[4566] = 6,
[4570] = 7,
[4483] = 20,
[4485] = 21,
[4487] = 22,
[4500] = 2,
[4501] = 23,
[4502] = 3,
[4503] = 24,
[4504] = 4,
[4505] = 25,
[4506] = 5,
[4507] = 26,
[4508] = 6,
[4509] = 27,
[4510] = 7,
[4511] = 28,
[4512] = 8,
[4513] = 29,
[4514] = 9,
[4515] = 30,
[4516] = 10,
[4517] = 31,
[4518] = 11,
[4519] = 32,
[4554] = 12,
[4555] = 33,
[4556] = 13,
[4557] = 34,
[4558] = 14,
[4559] = 35,
[4560] = 15,
[4561] = 36,
[4574] = 16,
[4575] = 17,
[4576] = 18,
[4577] = 19,
[4608] = 0,
[4609] = 1,
[4610] = 2,
[4612] = 3,
[4614] = 4,
[4648] = 5,
[4650] = 6,
[4652] = 7,
[4654] = 8,
[4656] = 9,
[4658] = 10,
[4660] = 11,
[4662] = 12,
[4664] = 13,
[4666] = 14,
[4668] = 15,
[4670] = 16,
[4672] = 17,
[4674] = 18,
[4676] = 19,
[4678] = 20,
[4680] = 21,
[4736] = 0,
[4737] = 1,
[4738] = 2,
[4740] = 3,
[4742] = 4,
[4756] = 5,
[4758] = 6,
[4760] = 7,
[4762] = 8,
[4764] = 9,
[4766] = 10,
[4768] = 11,
[4770] = 12,
[4772] = 13,
[4774] = 14,
[4792] = 15,
[4794] = 16,
[4796] = 17,
[4798] = 18,
[4800] = 19,
[4802] = 20,
[4804] = 21,
[4806] = 22,
[4808] = 23,
[4864] = 0,
[4865] = 1,
[4866] = 2,
[4868] = 3,
[4870] = 4,
[4904] = 5,
[4906] = 6,
[4908] = 7,
[4910] = 8,
[4912] = 9,
[4914] = 10,
[4916] = 11,
[4918] = 12,
[4938] = 13,
[4940] = 14,
[4942] = 15,
[4944] = 16,
[4992] = 0,
[4993] = 1,
[4994] = 2,
[4996] = 3,
[4998] = 4,
[5012] = 5,
[5014] = 6,
[5016] = 7,
[5018] = 8,
[5020] = 9,
[5022] = 10,
[5024] = 11,
[5026] = 12,
[5028] = 13,
[5030] = 14,
[5066] = 15,
[5068] = 16,
[5070] = 17,
[5072] = 18,
[5120] = 0,
[5121] = 1,
[5122] = 2,
[5124] = 3,
[5126] = 4,
[5160] = 8,
[5162] = 9,
[5164] = 10,
[5166] = 11,
[5168] = 12,
[5170] = 13,
[5172] = 14,
[5174] = 15,
[5176] = 16,
[5178] = 17,
[5180] = 18,
[5182] = 19,
[5184] = 20,
[5186] = 21,
[5188] = 22,
[5190] = 23,
[5192] = 24,
[5202] = 5,
[5206] = 6,
[5210] = 7,
[5248] = 0,
[5249] = 1,
[5250] = 2,
[5252] = 3,
[5254] = 4,
[5268] = 8,
[5270] = 9,
[5272] = 10,
[5274] = 11,
[5276] = 12,
[5278] = 13,
[5280] = 14,
[5282] = 15,
[5284] = 16,
[5286] = 17,
[5304] = 18,
[5306] = 19,
[5308] = 20,
[5310] = 21,
[5312] = 22,
[5314] = 23,
[5316] = 24,
[5318] = 25,
[5320] = 26,
[5330] = 5,
[5334] = 6,
[5338] = 7,
[5376] = 0,
[5377] = 1,
[5378] = 2,
[5380] = 3,
[5382] = 4,
[5416] = 8,
[5418] = 9,
[5420] = 10,
[5422] = 11,
[5424] = 12,
[5426] = 13,
[5428] = 14,
[5430] = 15,
[5450] = 16,
[5452] = 17,
[5454] = 18,
[5456] = 19,
[5458] = 5,
[5462] = 6,
[5466] = 7,
[5504] = 0,
[5505] = 1,
[5506] = 2,
[5508] = 3,
[5510] = 4,
[5524] = 8,
[5526] = 9,
[5528] = 10,
[5530] = 11,
[5532] = 12,
[5534] = 13,
[5536] = 14,
[5538] = 15,
[5540] = 16,
[5542] = 17,
[5578] = 18,
[5580] = 19,
[5582] = 20,
[5584] = 21,
[5586] = 5,
[5590] = 6,
[5594] = 7
[4611] = 20,
[4613] = 21,
[4615] = 22,
[4619] = 33,
[4621] = 34,
[4623] = 35,
[4625] = 36,
[4627] = 37,
[4628] = 2,
[4629] = 23,
[4630] = 3,
[4631] = 24,
[4632] = 4,
[4633] = 25,
[4634] = 5,
[4635] = 26,
[4636] = 6,
[4637] = 27,
[4638] = 7,
[4639] = 28,
[4640] = 8,
[4641] = 29,
[4642] = 9,
[4643] = 30,
[4644] = 10,
[4645] = 31,
[4646] = 11,
[4647] = 32,
[4682] = 12,
[4684] = 13,
[4686] = 14,
[4688] = 15,
[4702] = 16,
[4703] = 17,
[4704] = 18,
[4705] = 19,
[6144] = 0,
[6145] = 1,
[6146] = 2,
[6148] = 3,
[6150] = 4,
[6184] = 5,
[6186] = 6,
[6188] = 7,
[6190] = 8,
[6192] = 9,
[6194] = 10,
[6196] = 11,
[6198] = 12,
[6272] = 0,
[6273] = 1,
[6274] = 2,
[6276] = 3,
[6278] = 4,
[6292] = 5,
[6294] = 6,
[6296] = 7,
[6298] = 8,
[6300] = 9,
[6302] = 10,
[6304] = 11,
[6306] = 12,
[6308] = 13,
[6310] = 14,
[6400] = 0,
[6401] = 1,
[6402] = 2,
[6404] = 3,
[6406] = 4,
[6440] = 8,
[6442] = 9,
[6444] = 10,
[6446] = 11,
[6448] = 12,
[6450] = 13,
[6452] = 14,
[6454] = 15,
[6482] = 5,
[6486] = 6,
[6490] = 7,
[6528] = 0,
[6529] = 1,
[6530] = 2,
[6532] = 3,
[6534] = 4,
[6548] = 8,
[6550] = 9,
[6552] = 10,
[6554] = 11,
[6556] = 12,
[6558] = 13,
[6560] = 14,
[6562] = 15,
[6564] = 16,
[6566] = 17,
[6610] = 5,
[6614] = 6,
[6618] = 7,
[6656] = 0,
[6657] = 1,
[6658] = 2,
[6660] = 3,
[6662] = 4,
[6696] = 5,
[6698] = 6,
[6700] = 7,
[6702] = 8,
[6704] = 9,
[6706] = 10,
[6708] = 11,
[6710] = 12,
[6712] = 13,
[6714] = 14,
[6716] = 15,
[6718] = 16,
[6720] = 17,
[6722] = 18,
[6724] = 19,
[6726] = 20,
[6728] = 21,
[6784] = 0,
[6785] = 1,
[6786] = 2,
[6788] = 3,
[6790] = 4,
[6804] = 5,
[6806] = 6,
[6808] = 7,
[6810] = 8,
[6812] = 9,
[6814] = 10,
[6816] = 11,
[6818] = 12,
[6820] = 13,
[6822] = 14,
[6840] = 15,
[6842] = 16,
[6844] = 17,
[6846] = 18,
[6848] = 19,
[6850] = 20,
[6852] = 21,
[6854] = 22,
[6856] = 23,
[6912] = 0,
[6913] = 1,
[6914] = 2,
[6916] = 3,
[6918] = 4,
[6952] = 5,
[6954] = 6,
[6956] = 7,
[6958] = 8,
[6960] = 9,
[6962] = 10,
[6964] = 11,
[6966] = 12,
[6986] = 13,
[6988] = 14,
[6990] = 15,
[6992] = 16,
[7040] = 0,
[7041] = 1,
[7042] = 2,
[7044] = 3,
[7046] = 4,
[7060] = 5,
[7062] = 6,
[7064] = 7,
[7066] = 8,
[7068] = 9,
[7070] = 10,
[7072] = 11,
[7074] = 12,
[7076] = 13,
[7078] = 14,
[7114] = 15,
[7116] = 16,
[7118] = 17,
[7120] = 18,
[7168] = 0,
[7169] = 1,
[7170] = 2,
[7172] = 3,
[7174] = 4,
[7208] = 8,
[7210] = 9,
[7212] = 10,
[7214] = 11,
[7216] = 12,
[7218] = 13,
[7220] = 14,
[7222] = 15,
[7224] = 16,
[7226] = 17,
[7228] = 18,
[7230] = 19,
[7232] = 20,
[7234] = 21,
[7236] = 22,
[7238] = 23,
[7240] = 24,
[7250] = 5,
[7254] = 6,
[7258] = 7,
[7296] = 0,
[7297] = 1,
[7298] = 2,
[7300] = 3,
[7302] = 4,
[7316] = 8,
[7318] = 9,
[7320] = 10,
[7322] = 11,
[7324] = 12,
[7326] = 13,
[7328] = 14,
[7330] = 15,
[7332] = 16,
[7334] = 17,
[7352] = 18,
[7354] = 19,
[7356] = 20,
[7358] = 21,
[7360] = 22,
[7362] = 23,
[7364] = 24,
[7366] = 25,
[7368] = 26,
[7378] = 5,
[7382] = 6,
[7386] = 7,
[7424] = 0,
[7425] = 1,
[7426] = 2,
[7428] = 3,
[7430] = 4,
[7464] = 8,
[7466] = 9,
[7468] = 10,
[7470] = 11,
[7472] = 12,
[7474] = 13,
[7476] = 14,
[7478] = 15,
[7498] = 16,
[7500] = 17,
[7502] = 18,
[7504] = 19,
[7506] = 5,
[7510] = 6,
[7514] = 7,
[7552] = 0,
[7553] = 1,
[7554] = 2,
[7556] = 3,
[7558] = 4,
[7572] = 8,
[7574] = 9,
[7576] = 10,
[7578] = 11,
[7580] = 12,
[7582] = 13,
[7584] = 14,
[7586] = 15,
[7588] = 16,
[7590] = 17,
[7626] = 18,
[7628] = 19,
[7630] = 20,
[7632] = 21,
[7634] = 5,
[7638] = 6,
[7642] = 7
};

110
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Thu May 13 18:15:56 2021 */
/* date: Thu May 20 11:56:39 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@ -22,8 +22,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 0,
.cond_nums = 4 }
},
/* class_tid: 3, ingress */
[3] = {
/* class_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 15,
.start_tbl_idx = 12,
@ -32,8 +32,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
.cond_start_idx = 8,
.cond_nums = 1 }
},
/* class_tid: 4, egress */
[4] = {
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 6,
.start_tbl_idx = 27,
@ -306,7 +306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 38,
.result_num_fields = 5
},
{ /* class_tid: 3, , table: int_full_act_record.0 */
{ /* class_tid: 4, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@ -327,7 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 17
},
{ /* class_tid: 3, , table: port_table.wr_0 */
{ /* class_tid: 4, , table: port_table.wr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
@ -350,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 152,
.result_num_fields = 5
},
{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@ -372,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 0
},
{ /* class_tid: 3, , table: control.ing_0 */
{ /* class_tid: 4, , table: control.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@ -385,7 +385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
{ /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
{ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_RX,
@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 6,
.ident_nums = 1
},
{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 62,
.result_num_fields = 4
},
{ /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
{ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_RX,
@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
{ /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
{ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_RX,
@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
{ /* class_tid: 3, , table: control.egr_0 */
{ /* class_tid: 4, , table: control.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@ -485,7 +485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
{ /* class_tid: 3, , table: int_full_act_record.egr_0 */
{ /* class_tid: 4, , table: int_full_act_record.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@ -507,7 +507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
{ /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 0
},
{ /* class_tid: 3, , table: control.egr_1 */
{ /* class_tid: 4, , table: control.egr_1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
@ -542,7 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
{ /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
{ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.ident_start_idx = 7,
.ident_nums = 1
},
{ /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
{ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
{ /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
{ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@ -605,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
{ /* class_tid: 4, , table: int_full_act_record.loopback */
{ /* class_tid: 5, , table: int_full_act_record.loopback */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
{ /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
{ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_TX,
@ -645,7 +645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
{ /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
{ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
.direction = TF_DIR_TX,
@ -663,7 +663,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
{ /* class_tid: 4, , table: int_full_act_record.vf_ing */
{ /* class_tid: 5, , table: int_full_act_record.vf_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@ -685,7 +685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 17,
.encap_num_fields = 0
},
{ /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
{ /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.resource_sub_type =
@ -707,7 +707,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.result_num_fields = 0,
.encap_num_fields = 11
},
{ /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
{ /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@ -768,27 +768,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_O_L4
},
/* cond_reject: thor, class_tid: 3 */
/* cond_reject: thor, class_tid: 4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
/* cond_execute: class_tid: 3, control.ing_0 */
/* cond_execute: class_tid: 4, control.ing_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
/* cond_execute: class_tid: 3, control.egr_0 */
/* cond_execute: class_tid: 4, control.egr_0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
},
/* cond_execute: class_tid: 3, control.egr_1 */
/* cond_execute: class_tid: 4, control.egr_1 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
/* cond_reject: thor, class_tid: 4 */
/* cond_reject: thor, class_tid: 5 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
/* class_tid: 3, , table: port_table.wr_0 */
/* class_tid: 4, , table: port_table.wr_0 */
{
.field_info_mask = {
.description = "dev.port_id",
@ -3633,7 +3633,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
}
},
/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */
/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
{
.field_info_mask = {
.description = "svif",
@ -3653,7 +3653,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.field_info_mask = {
.description = "etype",
@ -3958,7 +3958,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.field_info_mask = {
.description = "svif",
@ -3978,7 +3978,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
}
},
/* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */
/* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */
{
.field_info_mask = {
.description = "svif",
@ -3998,7 +3998,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.field_info_mask = {
.description = "etype",
@ -5187,7 +5187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
/* class_tid: 3, , table: int_full_act_record.0 */
/* class_tid: 4, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
/* class_tid: 3, , table: port_table.wr_0 */
/* class_tid: 4, , table: port_table.wr_0 */
{
.description = "rid",
.field_bit_size = 32,
@ -5329,7 +5329,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@ -5380,7 +5380,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
/* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */
/* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
{
.description = "rid",
.field_bit_size = 32,
@ -5414,7 +5414,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */
/* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
/* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */
/* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@ -5434,7 +5434,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
/* class_tid: 3, , table: int_full_act_record.egr_0 */
/* class_tid: 4, , table: int_full_act_record.egr_0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@ -5542,7 +5542,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
@ -5593,7 +5593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
/* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */
/* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@ -5603,7 +5603,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
/* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */
/* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@ -5613,7 +5613,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
/* class_tid: 4, , table: int_full_act_record.loopback */
/* class_tid: 5, , table: int_full_act_record.loopback */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@ -5721,7 +5721,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
/* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */
/* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@ -5731,7 +5731,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
/* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */
/* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
.description = "act_rec_ptr",
.field_bit_size = 32,
@ -5741,7 +5741,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
/* class_tid: 4, , table: int_full_act_record.vf_ing */
/* class_tid: 5, , table: int_full_act_record.vf_ing */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@ -5849,7 +5849,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
/* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */
/* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
@ -5929,7 +5929,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
/* class_tid: 4, , table: int_full_act_record.vfr_egr0 */
/* class_tid: 5, , table: int_full_act_record.vfr_egr0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@ -6085,7 +6085,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */
/* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@ -6094,7 +6094,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_size = 10,
.ident_bit_pos = 29
},
/* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */
/* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
.description = "l2_cntxt_id",
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,

2
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Thu May 13 18:15:56 2021 */
/* date: Mon May 17 15:54:03 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"

3265
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
View File

File diff suppressed because it is too large Load Diff

42
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
View File

@ -413,11 +413,13 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt,
}
/* Update the parent counters if it is child flow */
if (sw_acc_tbl_entry->parent_flow_id) {
if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) {
uint32_t pc_idx;
/* Update the parent counters */
t_sw = sw_acc_tbl_entry;
if (ulp_flow_db_parent_flow_count_update(ctxt,
t_sw->parent_flow_id,
pc_idx = t_sw->pc_flow_idx & ~FLOW_CNTR_PC_FLOW_VALID;
if (ulp_flow_db_parent_flow_count_update(ctxt, pc_idx,
t_sw->pkt_count,
t_sw->byte_count)) {
PMD_DRV_LOG(ERR, "Error updating parent counters\n");
@ -658,6 +660,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0;
ulp_fc_info->num_entries--;
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
@ -688,6 +691,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
uint32_t hw_cntr_id = 0, sw_cntr_idx = 0;
struct sw_acc_counter *sw_acc_tbl_entry;
bool found_cntr_resource = false;
bool found_parent_flow = false;
uint32_t pc_idx = 0;
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
if (!ulp_fc_info)
@ -707,12 +712,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
(params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT ||
params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT ||
params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) {
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT)) {
found_cntr_resource = true;
break;
}
if (params.resource_func ==
BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
found_parent_flow = true;
pc_idx = params.resource_hndl;
}
} while (!rc && nxt_resource_index);
bnxt_ulp_cntxt_release_fdb_lock(ctxt);
@ -722,7 +731,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
dir = params.direction;
hw_cntr_id = params.resource_hndl;
if (params.resource_sub_type ==
if (!found_parent_flow &&
params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
if (!ulp_fc_info->num_counters)
return ulp_fc_tf_flow_stat_get(ctxt, &params, count);
@ -745,13 +755,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
sw_acc_tbl_entry->byte_count = 0;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
} else if (params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) {
} else if (found_parent_flow &&
params.resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
/* Get stats from the parent child table */
ulp_flow_db_parent_flow_count_get(ctxt, flow_id,
ulp_flow_db_parent_flow_count_get(ctxt, pc_idx,
&count->hits, &count->bytes,
count->reset);
if (count->hits)
count->hits_set = 1;
if (count->bytes)
count->bytes_set = 1;
} else {
/* TBD: Handle External counters */
@ -770,13 +783,13 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
*
* hw_cntr_id [in] The HW flow counter ID
*
* fid [in] parent flow id
* pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
uint32_t fid)
uint32_t pc_idx)
{
struct bnxt_ulp_fc_info *ulp_fc_info;
uint32_t sw_cntr_idx;
@ -789,10 +802,11 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
pthread_mutex_lock(&ulp_fc_info->fc_lock);
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) {
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid;
pc_idx |= FLOW_CNTR_PC_FLOW_VALID;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = pc_idx;
} else {
BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n",
hw_cntr_id, fid);
hw_cntr_id, pc_idx);
rc = -ENOENT;
}
pthread_mutex_unlock(&ulp_fc_info->fc_lock);

8
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
View File

@ -21,12 +21,14 @@
#define FLOW_CNTR_BYTES(v, d) (((v) & (d)->byte_count_mask) >> \
(d)->byte_count_shift)
#define FLOW_CNTR_PC_FLOW_VALID 0x1000000
struct sw_acc_counter {
uint64_t pkt_count;
uint64_t byte_count;
bool valid;
uint32_t hw_cntr_id;
uint32_t parent_flow_id;
uint32_t pc_flow_idx;
};
struct hw_fc_mem_info {
@ -175,12 +177,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx,
*
* hw_cntr_id [in] The HW flow counter ID
*
* fid [in] parent flow id
* pc_idx [in] parent child db index
*
*/
int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
uint32_t fid);
uint32_t pc_idx);
#endif /* _ULP_FC_MGR_H_ */

534
drivers/net/bnxt/tf_ulp/ulp_flow_db.c
View File

@ -386,101 +386,6 @@ ulp_flow_db_parent_tbl_deinit(struct bnxt_ulp_flow_db *flow_db)
}
}
/* internal validation function for parent flow tbl */
static struct bnxt_ulp_flow_db *
ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
uint32_t fid)
{
struct bnxt_ulp_flow_db *flow_db;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "Invalid Arguments\n");
return NULL;
}
/* check for max flows */
if (fid >= flow_db->flow_tbl.num_flows || !fid) {
BNXT_TF_DBG(ERR, "Invalid flow index\n");
return NULL;
}
/* No support for parent child db then just exit */
if (!flow_db->parent_child_db.entries_count) {
BNXT_TF_DBG(ERR, "parent child db not supported\n");
return NULL;
}
return flow_db;
}
/*
* Set the tunnel index in the parent flow
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_idx [in] The parent index of the parent flow entry
*
* returns index on success and negative on failure.
*/
static int32_t
ulp_flow_db_parent_tun_idx_set(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_idx, uint8_t tun_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "Invalid Arguments\n");
return -EINVAL;
}
/* check for parent idx validity */
p_pdb = &flow_db->parent_child_db;
if (parent_idx >= p_pdb->entries_count ||
!p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
return -EINVAL;
}
p_pdb->parent_flow_tbl[parent_idx].tun_idx = tun_idx;
return 0;
}
/*
* Get the tunnel index from the parent flow
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
*
* returns 0 if counter accum is set else -1.
*/
static int32_t
ulp_flow_db_parent_tun_idx_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid, uint8_t *tun_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
*tun_idx = p_pdb->parent_flow_tbl[idx].tun_idx;
return 0;
}
}
return -EINVAL;
}
/*
* Initialize the flow database. Memory is allocated in this
* call and assigned to the flow database.
@ -783,9 +688,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
struct bnxt_ulp_flow_tbl *flow_tbl;
struct ulp_fdb_resource_info *nxt_resource, *fid_resource;
uint32_t nxt_idx = 0;
struct bnxt_tun_cache_entry *tun_tbl;
uint8_t tun_idx = 0;
int rc;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
@ -862,18 +764,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
params->resource_hndl);
}
if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
if (!tun_tbl)
return -EINVAL;
rc = ulp_flow_db_parent_tun_idx_get(ulp_ctxt, fid, &tun_idx);
if (rc)
return rc;
ulp_clear_tun_entry(tun_tbl, tun_idx);
}
/* all good, return success */
return 0;
}
@ -892,7 +782,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
enum bnxt_ulp_fdb_type flow_type,
uint32_t fid)
{
struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_tbl *flow_tbl;
struct bnxt_ulp_flow_db *flow_db;
@ -934,12 +823,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
ulp_flow_db_func_id_set(flow_db, fid, 0);
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
if (!tun_tbl)
return -EINVAL;
ulp_clear_tun_inner_entry(tun_tbl, fid);
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid);
#endif
@ -1307,24 +1190,84 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
return 0;
}
/* internal validation function for parent flow tbl */
static struct ulp_fdb_parent_info *
ulp_flow_db_pc_db_entry_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t pc_idx)
{
struct bnxt_ulp_flow_db *flow_db;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "Invalid Arguments\n");
return NULL;
}
/* check for max flows */
if (pc_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
return NULL;
}
/* No support for parent child db then just exit */
if (!flow_db->parent_child_db.entries_count) {
BNXT_TF_DBG(ERR, "parent child db not supported\n");
return NULL;
}
if (!flow_db->parent_child_db.parent_flow_tbl[pc_idx].valid) {
BNXT_TF_DBG(ERR, "Not a valid tunnel index\n");
return NULL;
}
return &flow_db->parent_child_db.parent_flow_tbl[pc_idx];
}
/* internal validation function for parent flow tbl */
static struct bnxt_ulp_flow_db *
ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
uint32_t tun_idx)
{
struct bnxt_ulp_flow_db *flow_db;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "Invalid Arguments\n");
return NULL;
}
/* check for max flows */
if (tun_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) {
BNXT_TF_DBG(ERR, "Invalid tunnel index\n");
return NULL;
}
/* No support for parent child db then just exit */
if (!flow_db->parent_child_db.entries_count) {
BNXT_TF_DBG(ERR, "parent child db not supported\n");
return NULL;
}
return flow_db;
}
/*
* Allocate the entry in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
* fid [in] The flow id to the flow entry
* tun_idx [in] The tunnel index of the flow entry
*
* returns index on success and negative on failure.
*/
int32_t
ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
uint32_t fid)
static int32_t
ulp_flow_db_pc_db_idx_alloc(struct bnxt_ulp_context *ulp_ctxt,
uint32_t tun_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx, free_idx = 0;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, tun_idx);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
@ -1332,11 +1275,11 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
BNXT_TF_DBG(ERR, "fid is already allocated\n");
return -EINVAL;
if (p_pdb->parent_flow_tbl[idx].valid &&
p_pdb->parent_flow_tbl[idx].tun_idx == tun_idx) {
return idx;
}
if (!p_pdb->parent_flow_tbl[idx].parent_fid && !free_idx)
if (!p_pdb->parent_flow_tbl[idx].valid && !free_idx)
free_idx = idx + 1;
}
/* no free slots */
@ -1347,70 +1290,117 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
free_idx -= 1;
/* set the Fid in the parent child */
p_pdb->parent_flow_tbl[free_idx].parent_fid = fid;
p_pdb->parent_flow_tbl[free_idx].tun_idx = tun_idx;
p_pdb->parent_flow_tbl[free_idx].valid = 1;
return free_idx;
}
/*
* Free the entry in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
* fid [in] The flow id to the flow entry
* pc_entry [in] Ptr to parent child db entry
*
* returns 0 on success and negative on failure.
* returns none.
*/
static void
ulp_flow_db_pc_db_entry_free(struct bnxt_ulp_context *ulp_ctxt,
struct ulp_fdb_parent_info *pc_entry)
{
struct bnxt_tun_cache_entry *tun_tbl;
struct bnxt_ulp_flow_db *flow_db;
uint64_t *tmp_bitset;
/* free the tunnel entry */
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
if (tun_tbl)
ulp_tunnel_offload_entry_clear(tun_tbl, pc_entry->tun_idx);
/* free the child bitset*/
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (flow_db)
memset(pc_entry->child_fid_bitset, 0,
flow_db->parent_child_db.child_bitset_size);
/* free the contents */
tmp_bitset = pc_entry->child_fid_bitset;
memset(pc_entry, 0, sizeof(struct ulp_fdb_parent_info));
pc_entry->child_fid_bitset = tmp_bitset;
}
/*
* Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
* pc_idx [in] The index to parent child db
* parent_fid [in] The flow id of the parent flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
uint32_t fid)
ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
uint32_t pc_idx,
uint32_t parent_fid,
uint32_t set_flag)
{
struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
/* free the contents */
p_pdb->parent_flow_tbl[idx].parent_fid = 0;
memset(p_pdb->parent_flow_tbl[idx].child_fid_bitset,
0, p_pdb->child_bitset_size);
return 0;
}
}
BNXT_TF_DBG(ERR, "parent entry not found = %x\n", fid);
/* check for fid validity */
if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
return -EINVAL;
}
/* validate the arguments and parent child entry */
pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
if (!pc_entry) {
BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
if (set_flag) {
pc_entry->parent_fid = parent_fid;
} else {
if (pc_entry->parent_fid != parent_fid)
BNXT_TF_DBG(ERR, "Panic: invalid parent id\n");
pc_entry->parent_fid = 0;
/* Free the parent child db entry if no user present */
if (!pc_entry->f2_cnt)
ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
}
return 0;
}
/*
* Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
* pc_idx [in] The index to parent child db
* child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid,
ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
uint32_t pc_idx,
uint32_t child_fid,
uint32_t set_flag)
{
struct ulp_fdb_parent_info *pc_entry;
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx, a_idx;
uint32_t a_idx;
uint64_t *t;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
@ -1422,58 +1412,27 @@ ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
return -EINVAL;
}
p_pdb = &flow_db->parent_child_db;
a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
t = p_pdb->parent_flow_tbl[idx].child_fid_bitset;
if (set_flag)
ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
else
ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
return 0;
}
}
BNXT_TF_DBG(ERR, "Unable to set the parent-child flow %x:%x\n",
parent_fid, child_fid);
return -1;
}
/*
* Get the parent index from the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
* parent_idx [out] The parent index of parent flow entry
*
* returns zero on success and negative on failure.
*/
int32_t
ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid,
uint32_t *parent_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
/* validate the arguments and parent child entry */
pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
if (!pc_entry) {
BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
*parent_idx = idx;
a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
t = pc_entry->child_fid_bitset;
if (set_flag) {
ULP_INDEX_BITMAP_SET(t[a_idx], child_fid);
pc_entry->f2_cnt++;
} else {
ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid);
if (pc_entry->f2_cnt)
pc_entry->f2_cnt--;
if (!pc_entry->f2_cnt && !pc_entry->parent_fid)
ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry);
}
return 0;
}
}
BNXT_TF_DBG(ERR, "Unable to get the parent flow %x\n", parent_fid);
return -1;
}
/*
* Get the next child flow in the parent-child database
@ -1541,13 +1500,13 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
* Set the counter accumulation in the parent flow
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_idx [in] The parent index of the parent flow entry
* pc_idx [in] The parent child index of the parent flow entry
*
* returns index on success and negative on failure.
*/
static int32_t
ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_idx)
uint32_t pc_idx)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
@ -1560,50 +1519,16 @@ ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
/* check for parent idx validity */
p_pdb = &flow_db->parent_child_db;
if (parent_idx >= p_pdb->entries_count ||
!p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
if (pc_idx >= p_pdb->entries_count ||
!p_pdb->parent_flow_tbl[pc_idx].parent_fid) {
BNXT_TF_DBG(ERR, "Invalid parent child index %x\n", pc_idx);
return -EINVAL;
}
p_pdb->parent_flow_tbl[parent_idx].counter_acc = 1;
p_pdb->parent_flow_tbl[pc_idx].counter_acc = 1;
return 0;
}
/*
* Get the counter accumulation in the parent flow
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
*
* returns 0 if counter accum is set else -1.
*/
static int32_t
ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return -EINVAL;
}
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
if (p_pdb->parent_flow_tbl[idx].counter_acc)
return 0;
break;
}
}
return -1;
}
/*
* Orphan the child flow entry
* This is called only for child flows that have
@ -1677,22 +1602,30 @@ int32_t
ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
{
struct ulp_flow_db_res_params fid_parms;
uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC;
uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
struct ulp_flow_db_res_params res_params;
int32_t fid_idx, rc;
int32_t pc_idx;
/* create the child flow entry in parent flow table */
fid_idx = ulp_flow_db_parent_flow_alloc(parms->ulp_ctx, parms->fid);
if (fid_idx < 0) {
BNXT_TF_DBG(ERR, "Error in creating parent flow fid %x\n",
parms->fid);
return -1;
/* create or get the parent child database */
pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
if (pc_idx < 0) {
BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
parms->tun_idx);
return -EINVAL;
}
/* Update the parent fid */
if (ulp_flow_db_pc_db_parent_flow_set(parms->ulp_ctx, pc_idx,
parms->fid, 1)) {
BNXT_TF_DBG(ERR, "Error in setting parent fid %x\n",
parms->tun_idx);
return -EINVAL;
}
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW;
fid_parms.resource_hndl = fid_idx;
fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
if (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
parms->fid, &fid_parms)) {
@ -1710,20 +1643,13 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
&res_params)) {
/* Enable the counter accumulation in parent entry */
if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx,
fid_idx)) {
pc_idx)) {
BNXT_TF_DBG(ERR, "Error in setting counter acc %x\n",
parms->fid);
return -1;
}
}
rc = ulp_flow_db_parent_tun_idx_set(parms->ulp_ctx, fid_idx,
parms->tun_idx);
if (rc) {
BNXT_TF_DBG(ERR, "Error setting tun_idx in the parent flow\n");
return rc;
}
return 0;
}
@ -1741,12 +1667,18 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT;
enum bnxt_ulp_resource_func res_fun;
struct ulp_flow_db_res_params res_p;
uint32_t parent_fid = parms->parent_fid;
int32_t rc;
int32_t rc, pc_idx;
/* create or get the parent child database */
pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx);
if (pc_idx < 0) {
BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n",
parms->tun_idx);
return -1;
}
/* create the parent flow entry in parent flow table */
rc = ulp_flow_db_parent_child_flow_set(parms->ulp_ctx,
parms->parent_fid,
rc = ulp_flow_db_pc_db_child_flow_set(parms->ulp_ctx, pc_idx,
parms->fid, 1);
if (rc) {
BNXT_TF_DBG(ERR, "Error in setting child fid %x\n", parms->fid);
@ -1756,7 +1688,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
/* Add the parent details in the resource list of the flow */
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW;
fid_parms.resource_hndl = parms->parent_fid;
fid_parms.resource_hndl = pc_idx;
fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
BNXT_ULP_FDB_TYPE_REGULAR,
@ -1767,10 +1699,6 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
return rc;
}
/* check if accumulation count is set for parent flow */
rc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx,
parms->parent_fid);
if (!rc) {
/* check if internal count action included for this flow.*/
res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
@ -1784,13 +1712,13 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
res_p.direction,
res_p.resource_hndl,
parent_fid)) {
pc_idx)) {
BNXT_TF_DBG(ERR, "Error in setting child %x\n",
parms->fid);
return -1;
}
}
}
/* return success */
return 0;
}
@ -1799,7 +1727,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
* pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@ -1807,41 +1735,31 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid,
uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx;
struct ulp_fdb_parent_info *pc_entry;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
/* validate the arguments and get parent child entry */
pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
if (!pc_entry) {
BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
if (p_pdb->parent_flow_tbl[idx].counter_acc) {
p_pdb->parent_flow_tbl[idx].pkt_count +=
packet_count;
p_pdb->parent_flow_tbl[idx].byte_count +=
byte_count;
if (pc_entry->counter_acc) {
pc_entry->pkt_count += packet_count;
pc_entry->byte_count += byte_count;
}
return 0;
}
}
return -ENOENT;
}
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
* pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@ -1849,38 +1767,28 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid, uint64_t *packet_count,
uint32_t pc_idx, uint64_t *packet_count,
uint64_t *byte_count, uint8_t count_reset)
{
struct bnxt_ulp_flow_db *flow_db;
struct ulp_fdb_parent_child_db *p_pdb;
uint32_t idx;
struct ulp_fdb_parent_info *pc_entry;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
/* validate the arguments and get parent child entry */
pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx);
if (!pc_entry) {
BNXT_TF_DBG(ERR, "failed to get the parent child entry\n");
return -EINVAL;
}
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
if (p_pdb->parent_flow_tbl[idx].counter_acc) {
*packet_count =
p_pdb->parent_flow_tbl[idx].pkt_count;
*byte_count =
p_pdb->parent_flow_tbl[idx].byte_count;
if (pc_entry->counter_acc) {
*packet_count = pc_entry->pkt_count;
*byte_count = pc_entry->byte_count;
if (count_reset) {
p_pdb->parent_flow_tbl[idx].pkt_count = 0;
p_pdb->parent_flow_tbl[idx].byte_count = 0;
pc_entry->pkt_count = 0;
pc_entry->byte_count = 0;
}
}
return 0;
}
}
return -ENOENT;
}
/*
* reset the parent accumulation counters
@ -1897,7 +1805,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
uint32_t idx;
/* validate the arguments */
flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1);
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
if (!flow_db) {
BNXT_TF_DBG(ERR, "parent child db validation failed\n");
return;
@ -1905,7 +1813,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
p_pdb = &flow_db->parent_child_db;
for (idx = 0; idx < p_pdb->entries_count; idx++) {
if (p_pdb->parent_flow_tbl[idx].parent_fid &&
if (p_pdb->parent_flow_tbl[idx].valid &&
p_pdb->parent_flow_tbl[idx].counter_acc) {
p_pdb->parent_flow_tbl[idx].pkt_count = 0;
p_pdb->parent_flow_tbl[idx].byte_count = 0;

40
drivers/net/bnxt/tf_ulp/ulp_flow_db.h
View File

@ -58,6 +58,7 @@ struct bnxt_ulp_flow_tbl {
/* Structure to maintain parent-child flow relationships */
struct ulp_fdb_parent_info {
uint32_t valid;
uint32_t parent_fid;
uint32_t counter_acc;
uint64_t pkt_count;
@ -259,43 +260,36 @@ int32_t
ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
uint32_t flow_id,
uint16_t *cfa_action);
/*
* Allocate the entry in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
* fid [in] The flow id to the flow entry
*
* returns index on success and negative on failure.
*/
int32_t
ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
uint32_t fid);
/*
* Free the entry in the parent-child database
* Set or reset the parent flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
* fid [in] The flow id to the flow entry
* pc_idx [in] The index to parent child db
* parent_fid [in] The flow id of the parent flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns 0 on success and negative on failure.
* returns zero on success and negative on failure.
*/
int32_t
ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
uint32_t fid);
ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt,
uint32_t pc_idx,
uint32_t parent_fid,
uint32_t set_flag);
/*
* Set or reset the child flow in the parent-child database
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
* pc_idx [in] The index to parent child db
* child_fid [in] The flow id of the child flow entry
* set_flag [in] Use 1 for setting child, 0 to reset
*
* returns zero on success and negative on failure.
*/
int32_t
ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid,
ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
uint32_t pc_idx,
uint32_t child_fid,
uint32_t set_flag);
@ -368,7 +362,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
* Update the parent counters
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
* pc_idx [in] The parent flow entry idx
* packet_count [in] - packet count
* byte_count [in] - byte count
*
@ -376,14 +370,14 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
*/
int32_t
ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid,
uint32_t pc_idx,
uint64_t packet_count,
uint64_t byte_count);
/*
* Get the parent accumulation counters
*
* ulp_ctxt [in] Ptr to ulp_context
* parent_fid [in] The flow id of the parent flow entry
* pc_idx [in] The parent flow entry idx
* packet_count [out] - packet count
* byte_count [out] - byte count
*
@ -391,7 +385,7 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
*/
int32_t
ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t parent_fid,
uint32_t pc_idx,
uint64_t *packet_count,
uint64_t *byte_count,
uint8_t count_reset);

52
drivers/net/bnxt/tf_ulp/ulp_mapper.c
View File

@ -544,34 +544,14 @@ ulp_mapper_parent_flow_free(struct bnxt_ulp_context *ulp,
uint32_t parent_fid,
struct ulp_flow_db_res_params *res)
{
uint32_t idx, child_fid = 0, parent_idx;
struct bnxt_ulp_flow_db *flow_db;
uint32_t pc_idx;
parent_idx = (uint32_t)res->resource_hndl;
pc_idx = (uint32_t)res->resource_hndl;
/* check the validity of the parent fid */
if (ulp_flow_db_parent_flow_idx_get(ulp, parent_fid, &idx) ||
idx != parent_idx) {
BNXT_TF_DBG(ERR, "invalid parent flow id %x\n", parent_fid);
return -EINVAL;
}
/* Clear all the child flows parent index */
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp);
while (!ulp_flow_db_parent_child_flow_next_entry_get(flow_db, idx,
&child_fid)) {
/* update the child flows resource handle */
if (ulp_flow_db_child_flow_reset(ulp, BNXT_ULP_FDB_TYPE_REGULAR,
child_fid)) {
BNXT_TF_DBG(ERR, "failed to reset child flow %x\n",
child_fid);
return -EINVAL;
}
}
/* free the parent entry in the parent table flow */
if (ulp_flow_db_parent_flow_free(ulp, parent_fid)) {
BNXT_TF_DBG(ERR, "failed to free parent flow %x\n", parent_fid);
/* reset the child flow bitset*/
if (ulp_flow_db_pc_db_parent_flow_set(ulp, pc_idx, parent_fid, 0)) {
BNXT_TF_DBG(ERR, "error in reset parent flow bitset %x:%x\n",
pc_idx, parent_fid);
return -EINVAL;
}
return 0;
@ -582,16 +562,14 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp,
uint32_t child_fid,
struct ulp_flow_db_res_params *res)
{
uint32_t parent_fid;
uint32_t pc_idx;
parent_fid = (uint32_t)res->resource_hndl;
if (!parent_fid)
return 0; /* Already freed - orphan child*/
pc_idx = (uint32_t)res->resource_hndl;
/* reset the child flow bitset*/
if (ulp_flow_db_parent_child_flow_set(ulp, parent_fid, child_fid, 0)) {
if (ulp_flow_db_pc_db_child_flow_set(ulp, pc_idx, child_fid, 0)) {
BNXT_TF_DBG(ERR, "error in resetting child flow bitset %x:%x\n",
parent_fid, child_fid);
pc_idx, child_fid);
return -EINVAL;
}
return 0;
@ -1944,6 +1922,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
/* If only allocation of identifier then perform and exit */
if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT) {
rc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl);
return rc;
}
kflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds);
if (!kflds || !num_kflds) {
BNXT_TF_DBG(ERR, "Failed to get key fields\n");
@ -3889,7 +3873,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.class_tid = cparms->class_tid;
parms.flow_type = cparms->flow_type;
parms.parent_flow = cparms->parent_flow;
parms.parent_fid = cparms->parent_fid;
parms.child_flow = cparms->child_flow;
parms.fid = cparms->flow_id;
parms.tun_idx = cparms->tun_idx;
parms.app_priority = cparms->app_priority;
@ -3954,7 +3938,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
rc = ulp_flow_db_parent_flow_create(&parms);
if (rc)
goto flow_error;
} else if (parms.parent_fid) {
} else if (parms.child_flow) {
/* create a child flow details */
rc = ulp_flow_db_child_flow_create(&parms);
if (rc)

6
drivers/net/bnxt/tf_ulp/ulp_mapper.h
View File

@ -53,7 +53,7 @@ struct bnxt_ulp_mapper_parms {
enum bnxt_ulp_fdb_type flow_type;
struct bnxt_ulp_mapper_data *mapper_data;
struct bnxt_ulp_device_params *device_params;
uint32_t parent_fid;
uint32_t child_flow;
uint32_t parent_flow;
uint8_t tun_idx;
uint32_t app_priority;
@ -79,8 +79,8 @@ struct bnxt_ulp_mapper_create_parms {
enum bnxt_ulp_fdb_type flow_type;
uint32_t flow_id;
/* if set then create it as a child flow with parent as parent_fid */
uint32_t parent_fid;
/* if set then create it as a child flow */
uint32_t child_flow;
/* if set then create a parent flow */
uint32_t parent_flow;
uint8_t tun_idx;

31
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
View File

@ -215,6 +215,21 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
}
};
struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = {
[BNXT_RTE_FLOW_ACTION_TYPE_END - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
.act_type = BNXT_ULP_ACT_TYPE_END,
.proto_act_func = NULL
},
[BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_vendor_vxlan_decap_act_handler
},
[BNXT_RTE_FLOW_ACTION_TYPE_LAST - BNXT_RTE_FLOW_ACTION_TYPE_END] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
}
};
/*
* This table has to be indexed based on the rte_flow_item_type that is part of
* DPDK. The below array is list of parsing functions for each of the flow items
@ -414,3 +429,19 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.proto_hdr_func = NULL
}
};
struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[] = {
[BNXT_RTE_FLOW_ITEM_TYPE_END - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
.hdr_type = BNXT_ULP_HDR_TYPE_END,
.proto_hdr_func = NULL
},
[BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_vendor_vxlan_decap_hdr_handler
},
[BNXT_RTE_FLOW_ITEM_TYPE_LAST - BNXT_RTE_FLOW_ITEM_TYPE_END] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
};

130
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
View File

@ -125,13 +125,21 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
/* Parse all the items in the pattern */
while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
/* get the header information from the flow_hdr_info table */
if (item->type >= (uint32_t)
BNXT_RTE_FLOW_ITEM_TYPE_END) {
if (item->type >=
(uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST)
goto hdr_parser_error;
/* get the header information */
hdr_info = &ulp_vendor_hdr_info[item->type -
BNXT_RTE_FLOW_ITEM_TYPE_END];
} else {
if (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2)
goto hdr_parser_error;
hdr_info = &ulp_hdr_info[item->type];
}
if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_NOT_SUPPORTED) {
BNXT_TF_DBG(ERR,
"Truflow parser does not support type %d\n",
item->type);
return BNXT_TF_RC_PARSE_ERR;
goto hdr_parser_error;
} else if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_hdr_func) {
@ -145,6 +153,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
}
/* update the implied SVIF */
return ulp_rte_parser_implicit_match_port_process(params);
hdr_parser_error:
BNXT_TF_DBG(ERR, "Truflow parser does not support type %d\n",
item->type);
return BNXT_TF_RC_PARSE_ERR;
}
/*
@ -160,16 +173,23 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* Parse all the items in the pattern */
while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
/* get the header information from the flow_hdr_info table */
if (action_item->type >=
(uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) {
if (action_item->type >=
(uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST)
goto act_parser_error;
/* get the header information from bnxt actinfo table */
hdr_info = &ulp_vendor_act_info[action_item->type -
BNXT_RTE_FLOW_ACTION_TYPE_END];
} else {
if (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED)
goto act_parser_error;
/* get the header information from the act info table */
hdr_info = &ulp_act_info[action_item->type];
if (hdr_info->act_type ==
BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
BNXT_TF_DBG(ERR,
"Truflow parser does not support act %u\n",
action_item->type);
return BNXT_TF_RC_ERROR;
} else if (hdr_info->act_type ==
BNXT_ULP_ACT_TYPE_SUPPORTED) {
}
if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) {
goto act_parser_error;
} else if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_SUPPORTED) {
/* call the registered callback handler */
if (hdr_info->proto_act_func) {
if (hdr_info->proto_act_func(action_item,
@ -184,6 +204,11 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/* update the implied port details */
ulp_rte_parser_implicit_act_port_process(params);
return BNXT_TF_RC_SUCCESS;
act_parser_error:
BNXT_TF_DBG(ERR, "Truflow parser does not support act %u\n",
action_item->type);
return BNXT_TF_RC_ERROR;
}
/*
@ -325,11 +350,10 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
/*
* Function to handle the post processing of the parsing details
*/
int32_t
void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
{
ulp_post_process_normal_flow(params);
return ulp_post_process_tun_flow(params);
}
/*
@ -660,7 +684,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
{
const struct rte_flow_item_eth *eth_spec = item->spec;
const struct rte_flow_item_eth *eth_mask = item->mask;
uint32_t idx = 0;
uint32_t idx = 0, dmac_idx = 0;
uint32_t size;
uint16_t eth_type = 0;
uint32_t inner_flag = 0;
@ -686,6 +710,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
* Copy the rte_flow_item for eth into hdr_field using ethernet
* header fields
*/
dmac_idx = idx;
size = sizeof(((struct rte_flow_item_eth *)NULL)->dst.addr_bytes);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(eth_spec, dst.addr_bytes),
@ -719,6 +744,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
inner_flag = 1;
} else {
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID,
dmac_idx);
}
/* Update the field protocol hdr bitmap */
ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
@ -926,7 +953,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv4 *ipv4_spec = item->spec;
const struct rte_flow_item_ipv4 *ipv4_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
uint32_t idx = 0;
uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint8_t proto = 0;
uint32_t inner_flag = 0;
@ -939,22 +966,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_O_ETH) &&
!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_I_ETH)) {
/* Since F2 flow does not include eth item, when parser detects
* IPv4/IPv6 item list and it belongs to the outer header; i.e.,
* o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
* then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
* This will allow the parser post processor to update the
* t_dmac in hdr_field[o_eth.dmac]
*/
idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
BNXT_ULP_PROTO_HDR_VLAN_NUM);
params->field_idx = idx;
}
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV4_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@ -1033,6 +1044,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv4_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv4_spec, hdr.dst_addr),
@ -1048,6 +1060,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
/* Update the tunnel offload dest ip offset */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
dip_idx);
}
/* Some of the PMD applications may set the protocol field
@ -1071,7 +1086,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv6 *ipv6_spec = item->spec;
const struct rte_flow_item_ipv6 *ipv6_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
uint32_t idx = 0;
uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint32_t ver_spec = 0, ver_mask = 0;
uint32_t tc_spec = 0, tc_mask = 0;
@ -1087,22 +1102,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_O_ETH) &&
!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_I_ETH)) {
/* Since F2 flow does not include eth item, when parser detects
* IPv4/IPv6 item list and it belongs to the outer header; i.e.,
* o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
* then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
* This will allow the parser post processor to update the
* t_dmac in hdr_field[o_eth.dmac]
*/
idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
BNXT_ULP_PROTO_HDR_VLAN_NUM);
params->field_idx = idx;
}
if (ulp_rte_prsr_fld_size_validate(params, &idx,
BNXT_ULP_PROTO_HDR_IPV6_NUM)) {
BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
@ -1171,6 +1170,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_deference_struct(ipv6_mask, hdr.src_addr),
ULP_PRSR_ACT_DEFAULT);
dip_idx = idx;
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.dst_addr);
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv6_spec, hdr.dst_addr),
@ -1186,6 +1186,9 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
/* Update the tunnel offload dest ip offset */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID,
dip_idx);
}
/* Update the field protocol hdr bitmap */
@ -1200,9 +1203,11 @@ static void
ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
uint16_t dst_port)
{
if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN))
if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
BNXT_ULP_HDR_BIT_T_VXLAN);
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
}
if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_T_VXLAN) ||
@ -2484,3 +2489,24 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
return ret;
}
/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */
int32_t
ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params)
{
/* Set the F1 flow header bit */
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
return ulp_rte_vxlan_decap_act_handler(action_item, params);
}
/* Function to handle the parsing of bnxt vendor Flow item vxlan Header. */
int32_t
ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params)
{
RTE_SET_USED(item);
/* Set the F2 flow header bit */
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2);
return ulp_rte_vxlan_decap_act_handler(NULL, params);
}

10
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
View File

@ -75,7 +75,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
/*
* Function to handle the post processing of the parsing details
*/
int32_t
void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params);
/* Function to handle the parsing of RTE Flow item PF Header. */
@ -270,4 +270,12 @@ int32_t
ulp_rte_shared_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
int32_t
ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
int32_t
ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params);
#endif /* _ULP_RTE_PARSER_H_ */

10
drivers/net/bnxt/tf_ulp/ulp_template_struct.h
View File

@ -78,17 +78,19 @@ struct ulp_rte_parser_params {
uint32_t priority;
uint32_t fid;
uint32_t parent_flow;
uint32_t parent_fid;
uint32_t child_flow;
uint16_t func_id;
uint16_t port_id;
uint32_t class_id;
uint32_t act_tmpl;
struct bnxt_ulp_context *ulp_ctx;
uint32_t hdr_sig_id;
uint32_t flow_sig_id;
uint64_t flow_sig_id;
uint32_t flow_pattern_id;
uint32_t act_pattern_id;
uint8_t app_id;
uint8_t tun_idx;
};
/* Flow Parser Header Information Structure */
@ -101,6 +103,7 @@ struct bnxt_ulp_rte_hdr_info {
/* Flow Parser Header Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_hdr_info ulp_hdr_info[];
extern struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[];
/* Flow Parser Action Information Structure */
struct bnxt_ulp_rte_act_info {
@ -113,6 +116,7 @@ struct bnxt_ulp_rte_act_info {
/* Flow Parser Action Information Structure Array defined in template source*/
extern struct bnxt_ulp_rte_act_info ulp_act_info[];
extern struct bnxt_ulp_rte_act_info ulp_vendor_act_info[];
/* Flow Matcher structures */
struct bnxt_ulp_header_match_info {
@ -136,7 +140,7 @@ struct bnxt_ulp_class_match_info {
uint8_t wc_pri;
uint8_t app_sig;
uint32_t hdr_sig_id;
uint32_t flow_sig_id;
uint64_t flow_sig_id;
uint32_t flow_pattern_id;
};

541
drivers/net/bnxt/tf_ulp/ulp_tun.c
View File

@ -3,225 +3,111 @@
* All rights reserved.
*/
#include <sys/queue.h>
#include <rte_malloc.h>
#include "bnxt.h"
#include "bnxt_ulp.h"
#include "ulp_tun.h"
#include "ulp_rte_parser.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "ulp_matcher.h"
#include "ulp_mapper.h"
#include "ulp_flow_db.h"
#include "ulp_utils.h"
/* This function programs the outer tunnel flow in the hardware. */
static int32_t
ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry *tun_entry,
uint16_t tun_idx)
/* returns negative on error, 1 if new entry is allocated or zero if old */
int32_t
ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
struct rte_flow_tunnel *app_tunnel,
struct bnxt_flow_app_tun_ent **tun_entry)
{
struct bnxt_ulp_mapper_create_parms mparms = { 0 };
int ret;
struct bnxt_flow_app_tun_ent *tun_ent_list;
int32_t i, rc = 0, free_entry = -1;
/* Reset the JUMP action bit in the action bitmap as we don't
* offload this action.
*/
ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
/* Dump the rte flow pattern */
ulp_parser_hdr_info_dump(params);
/* Dump the rte flow action */
ulp_parser_act_info_dump(params);
#endif
#endif
ret = ulp_matcher_pattern_match(params, &params->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
goto err;
ret = ulp_matcher_action_match(params, &params->act_tmpl);
if (ret != BNXT_TF_RC_SUCCESS)
goto err;
params->parent_flow = true;
bnxt_ulp_init_mapper_params(&mparms, params,
BNXT_ULP_FDB_TYPE_REGULAR);
mparms.tun_idx = tun_idx;
/* Call the ulp mapper to create the flow in the hardware. */
ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);
if (ret)
goto err;
/* Store the tunnel dmac in the tunnel cache table and use it while
* programming tunnel inner flow.
*/
memcpy(tun_entry->t_dmac,
&params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec,
RTE_ETHER_ADDR_LEN);
tun_entry->tun_flow_info[params->port_id].state =
BNXT_ULP_FLOW_STATE_TUN_O_OFFLD;
tun_entry->outer_tun_flow_id = params->fid;
/* Tunnel outer flow and it's related inner flows are correlated
* based on Tunnel Destination IP Address.
*/
if (tun_entry->t_dst_ip_valid)
goto done;
if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
memcpy(&tun_entry->t_dst_ip,
&params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
sizeof(rte_be32_t));
else
memcpy(tun_entry->t_dst_ip6,
&params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
sizeof(tun_entry->t_dst_ip6));
tun_entry->t_dst_ip_valid = true;
done:
return BNXT_TF_RC_FID;
err:
memset(tun_entry, 0, sizeof(struct bnxt_tun_cache_entry));
return BNXT_TF_RC_ERROR;
tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
if (!tun_ent_list) {
BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
return -EINVAL;
}
/* This function programs the inner tunnel flow in the hardware. */
static void
ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry,
struct ulp_rte_parser_params *tun_o_params)
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
if (!tun_ent_list[i].ref_cnt) {
if (free_entry < 0)
free_entry = i;
} else {
if (!memcmp(&tun_ent_list[i].app_tunnel,
app_tunnel,
sizeof(struct rte_flow_tunnel))) {
*tun_entry = &tun_ent_list[i];
tun_ent_list[free_entry].ref_cnt++;
return rc;
}
}
}
if (free_entry >= 0) {
*tun_entry = &tun_ent_list[free_entry];
memcpy(&tun_ent_list[free_entry].app_tunnel, app_tunnel,
sizeof(struct rte_flow_tunnel));
tun_ent_list[free_entry].ref_cnt = 1;
rc = 1;
} else {
BNXT_TF_DBG(ERR, "ulp app tunnel list is full\n");
return -ENOMEM;
}
return rc;
}
void
ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry)
{
struct bnxt_ulp_mapper_create_parms mparms = { 0 };
struct ulp_per_port_flow_info *flow_info;
struct ulp_rte_parser_params *inner_params;
int ret;
/* Tunnel inner flow doesn't have tunnel dmac, use the tunnel
* dmac that was stored during F1 programming.
*/
flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id];
STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) {
memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
inner_params->parent_fid = tun_entry->outer_tun_flow_id;
bnxt_ulp_init_mapper_params(&mparms, inner_params,
BNXT_ULP_FDB_TYPE_REGULAR);
ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms);
if (ret)
PMD_DRV_LOG(ERR,
"Failed to create inner tun flow, FID:%u.",
inner_params->fid);
if (tun_entry) {
if (tun_entry->ref_cnt) {
tun_entry->ref_cnt--;
if (!tun_entry->ref_cnt)
memset(tun_entry, 0,
sizeof(struct bnxt_flow_app_tun_ent));
}
}
}
/* This function either install outer tunnel flow & inner tunnel flow
* or just the outer tunnel flow based on the flow state.
*/
static int32_t
ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry *tun_entry,
uint16_t tun_idx)
int32_t
ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry)
{
int ret;
if (!tun_entry)
return -EINVAL;
ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx);
if (ret == BNXT_TF_RC_ERROR) {
PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow.");
return ret;
tun_entry->action.type = (typeof(tun_entry->action.type))
BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP;
tun_entry->action.conf = tun_entry;
return 0;
}
/* Install any cached tunnel inner flows that came before tunnel
* outer flow.
*/
ulp_install_inner_tun_flow(tun_entry, params);
return BNXT_TF_RC_FID;
}
/* This function will be called if inner tunnel flow request comes before
* outer tunnel flow request.
*/
static int32_t
ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry *tun_entry)
int32_t
ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry)
{
struct ulp_rte_parser_params *inner_tun_params;
struct ulp_per_port_flow_info *flow_info;
int ret;
if (!tun_entry)
return -EINVAL;
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER
/* Dump the rte flow pattern */
ulp_parser_hdr_info_dump(params);
/* Dump the rte flow action */
ulp_parser_act_info_dump(params);
#endif
#endif
ret = ulp_matcher_pattern_match(params, &params->class_id);
if (ret != BNXT_TF_RC_SUCCESS)
return BNXT_TF_RC_ERROR;
ret = ulp_matcher_action_match(params, &params->act_tmpl);
if (ret != BNXT_TF_RC_SUCCESS)
return BNXT_TF_RC_ERROR;
/* If Tunnel inner flow comes first then we can't install it in the
* hardware, because, Tunnel inner flow will not have L2 context
* information. So, just cache the Tunnel inner flow information
* and program it in the context of F1 flow installation.
*/
flow_info = &tun_entry->tun_flow_info[params->port_id];
inner_tun_params = rte_zmalloc("ulp_inner_tun_params",
sizeof(struct ulp_rte_parser_params), 0);
if (!inner_tun_params)
return BNXT_TF_RC_ERROR;
memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params));
STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params,
next);
flow_info->tun_i_cnt++;
/* F1 and it's related Tunnel inner flows are correlated based on
* Tunnel Destination IP Address. It could be already set, if
* the inner flow got offloaded first.
*/
if (tun_entry->t_dst_ip_valid)
goto done;
if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
memcpy(&tun_entry->t_dst_ip,
&params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
sizeof(rte_be32_t));
else
memcpy(tun_entry->t_dst_ip6,
&params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
sizeof(tun_entry->t_dst_ip6));
tun_entry->t_dst_ip_valid = true;
done:
return BNXT_TF_RC_FID;
tun_entry->item.type = (typeof(tun_entry->item.type))
BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP;
tun_entry->item.spec = tun_entry;
tun_entry->item.last = NULL;
tun_entry->item.mask = NULL;
return 0;
}
/* This function will be called if inner tunnel flow request comes after
* the outer tunnel flow request.
*/
static int32_t
ulp_post_process_inner_tun_flow(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry *tun_entry)
struct bnxt_flow_app_tun_ent *
ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx,
const void *ctx)
{
memcpy(&params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
struct bnxt_flow_app_tun_ent *tun_ent_list;
int32_t i;
params->parent_fid = tun_entry->outer_tun_flow_id;
tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx);
if (!tun_ent_list) {
BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n");
return NULL;
}
return BNXT_TF_RC_NORMAL;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
if (&tun_ent_list[i] == ctx)
return &tun_ent_list[i];
}
return NULL;
}
static int32_t
@ -229,203 +115,116 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params,
struct bnxt_tun_cache_entry **tun_entry,
uint16_t *tun_idx)
{
int i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
int32_t i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
struct bnxt_tun_cache_entry *tun_tbl;
bool tun_entry_found = false, free_entry_found = false;
uint32_t dip_idx, dmac_idx, use_ipv4 = 0;
tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(params->ulp_ctx);
if (!tun_tbl)
if (!tun_tbl) {
BNXT_TF_DBG(ERR, "Error: could not get Tunnel table\n");
return BNXT_TF_RC_ERROR;
}
/* get the outer destination ip field index */
dip_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID);
dmac_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID);
if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
use_ipv4 = 1;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
if (!memcmp(&tun_tbl[i].t_dst_ip,
&params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
sizeof(rte_be32_t)) ||
!memcmp(&tun_tbl[i].t_dst_ip6,
&params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
16)) {
tun_entry_found = true;
break;
}
if (!tun_tbl[i].t_dst_ip_valid && !free_entry_found) {
if (!tun_tbl[i].t_dst_ip_valid) {
if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
first_free_entry = i;
free_entry_found = true;
continue;
}
}
if (tun_entry_found) {
/* match on the destination ip of the tunnel */
if ((use_ipv4 && !memcmp(&tun_tbl[i].t_dst_ip,
params->hdr_field[dip_idx].spec,
sizeof(rte_be32_t))) ||
(!use_ipv4 &&
!memcmp(tun_tbl[i].t_dst_ip6,
params->hdr_field[dip_idx].spec,
sizeof(((struct bnxt_tun_cache_entry *)
NULL)->t_dst_ip6)))) {
*tun_entry = &tun_tbl[i];
*tun_idx = i;
} else {
if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
return BNXT_TF_RC_ERROR;
*tun_entry = &tun_tbl[first_free_entry];
*tun_idx = first_free_entry;
return 0;
}
}
if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) {
BNXT_TF_DBG(ERR, "Error: No entry available in tunnel table\n");
return BNXT_TF_RC_ERROR;
}
*tun_idx = first_free_entry;
*tun_entry = &tun_tbl[first_free_entry];
tun_tbl[first_free_entry].t_dst_ip_valid = true;
/* Update the destination ip and mac */
if (use_ipv4)
memcpy(&tun_tbl[first_free_entry].t_dst_ip,
params->hdr_field[dip_idx].spec, sizeof(rte_be32_t));
else
memcpy(tun_tbl[first_free_entry].t_dst_ip6,
params->hdr_field[dip_idx].spec,
sizeof(((struct bnxt_tun_cache_entry *)
NULL)->t_dst_ip6));
memcpy(tun_tbl[first_free_entry].t_dmac,
params->hdr_field[dmac_idx].spec, RTE_ETHER_ADDR_LEN);
return 0;
}
int32_t
ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
/* Tunnel API to delete the tunnel entry */
void
ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
uint8_t tun_idx)
{
memset(&tun_tbl[tun_idx], 0, sizeof(struct bnxt_tun_cache_entry));
}
/* Tunnel API to perform tunnel offload process when there is F1/F2 flows */
int32_t
ulp_tunnel_offload_process(struct ulp_rte_parser_params *params)
{
bool inner_tun_sig, cache_inner_tun_flow;
bool outer_tun_reject, outer_tun_flow, inner_tun_flow;
enum bnxt_ulp_tun_flow_state flow_state;
struct bnxt_tun_cache_entry *tun_entry;
uint32_t l3_tun, l3_tun_decap;
uint16_t tun_idx;
int rc;
int32_t rc = BNXT_TF_RC_SUCCESS;
/* Computational fields that indicate it's a TUNNEL DECAP flow */
l3_tun = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN);
l3_tun_decap = ULP_COMP_FLD_IDX_RD(params,
BNXT_ULP_CF_IDX_L3_TUN_DECAP);
if (!l3_tun)
return BNXT_TF_RC_NORMAL;
/* Perform the tunnel offload only for F1 and F2 flows */
if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_F1) &&
!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_F2))
return rc;
/* search for the tunnel entry if not found create one */
rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
if (rc == BNXT_TF_RC_ERROR)
return rc;
if (params->port_id >= RTE_MAX_ETHPORTS)
return BNXT_TF_RC_ERROR;
flow_state = tun_entry->tun_flow_info[params->port_id].state;
/* Outer tunnel flow validation */
outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params);
outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state,
outer_tun_flow);
/* Inner tunnel flow validation */
inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params);
cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state,
inner_tun_sig);
inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig);
if (outer_tun_reject) {
tun_entry->outer_tun_rej_cnt++;
BNXT_TF_DBG(ERR,
"Tunnel F1 flow rejected, COUNT: %d\n",
tun_entry->outer_tun_rej_cnt);
}
if (outer_tun_reject)
return BNXT_TF_RC_ERROR;
else if (cache_inner_tun_flow)
return ulp_post_process_cache_inner_tun_flow(params, tun_entry);
else if (outer_tun_flow)
return ulp_post_process_outer_tun_flow(params, tun_entry,
tun_idx);
else if (inner_tun_flow)
return ulp_post_process_inner_tun_flow(params, tun_entry);
else
return BNXT_TF_RC_NORMAL;
}
void
ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl)
{
struct ulp_per_port_flow_info *flow_info;
int i, j;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
flow_info = &tun_tbl[i].tun_flow_info[j];
STAILQ_INIT(&flow_info->tun_i_prms_list);
}
}
}
void
ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx)
{
struct ulp_rte_parser_params *inner_params;
struct ulp_per_port_flow_info *flow_info;
int j;
for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
STAILQ_FOREACH(inner_params,
&flow_info->tun_i_prms_list,
next) {
STAILQ_REMOVE(&flow_info->tun_i_prms_list,
inner_params,
ulp_rte_parser_params, next);
rte_free(inner_params);
}
}
memset(&tun_tbl[tun_idx], 0,
sizeof(struct bnxt_tun_cache_entry));
for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
flow_info = &tun_tbl[tun_idx].tun_flow_info[j];
STAILQ_INIT(&flow_info->tun_i_prms_list);
}
}
static bool
ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry,
struct ulp_per_port_flow_info *flow_info,
uint32_t fid)
{
struct ulp_rte_parser_params *inner_params;
int j;
STAILQ_FOREACH(inner_params,
&flow_info->tun_i_prms_list,
next) {
if (inner_params->fid == fid) {
STAILQ_REMOVE(&flow_info->tun_i_prms_list,
inner_params,
ulp_rte_parser_params,
next);
rte_free(inner_params);
flow_info->tun_i_cnt--;
/* When a dpdk application offloads a duplicate
* tunnel inner flow on a port that it is not
* destined to, there won't be a tunnel outer flow
* associated with these duplicate tunnel inner flows.
* So, when the last tunnel inner flow ages out, the
* driver has to clear the tunnel entry, otherwise
* the tunnel entry cannot be reused.
/* Tunnel offload for the outer Tunnel flow */
if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_F1)) {
/* Reset the JUMP action bit in the action bitmap as we don't
* offload this action.
*/
if (!flow_info->tun_i_cnt &&
flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) {
memset(tun_entry, 0,
sizeof(struct bnxt_tun_cache_entry));
for (j = 0; j < RTE_MAX_ETHPORTS; j++)
STAILQ_INIT(&flow_info->tun_i_prms_list);
}
return true;
}
}
return false;
}
/* When a dpdk application offloads the same tunnel inner flow
* on all the uplink ports, a tunnel inner flow entry is cached
* even if it is not for the right uplink port. Such tunnel
* inner flows will eventually get aged out as there won't be
* any traffic on these ports. When such a flow destroy is
* called, cleanup the tunnel inner flow entry.
*/
void
ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid)
{
struct ulp_per_port_flow_info *flow_info;
int i, j;
for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
if (!tun_tbl[i].t_dst_ip_valid)
continue;
for (j = 0; j < RTE_MAX_ETHPORTS; j++) {
flow_info = &tun_tbl[i].tun_flow_info[j];
if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i],
flow_info, fid) == true)
return;
}
ULP_BITMAP_RESET(params->act_bitmap.bits,
BNXT_ULP_ACT_BIT_JUMP);
params->parent_flow = true;
params->tun_idx = tun_idx;
tun_entry->outer_tun_flow_id = params->fid;
} else if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_F2)) {
ULP_BITMAP_RESET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_F2);
/* add the vxlan decap action for F2 flows */
ULP_BITMAP_SET(params->act_bitmap.bits,
BNXT_ULP_ACT_BIT_VXLAN_DECAP);
params->child_flow = true;
params->tun_idx = tun_idx;
params->parent_flow = false;
}
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUNNEL_ID, tun_idx);
return rc;
}

89
drivers/net/bnxt/tf_ulp/ulp_tun.h
View File

@ -8,7 +8,6 @@
#include <inttypes.h>
#include <stdbool.h>
#include <sys/queue.h>
#include "rte_version.h"
#include "rte_ethdev.h"
@ -16,60 +15,6 @@
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \
((l3_tun) && \
ULP_BITMAP_ISSET((params)->act_bitmap.bits, \
BNXT_ULP_ACT_BIT_JUMP))
#define BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params) \
((l3_tun) && (l3_tun_decap) && \
!ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \
BNXT_ULP_HDR_BIT_O_ETH))
#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \
((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig))
#define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \
((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig))
/* It is invalid to get another outer flow offload request
* for the same tunnel, while the outer flow is already offloaded.
*/
#define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \
((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig))
#define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1
#define ULP_TUN_O_IPV4_DIP_INDEX 19
#define ULP_TUN_O_IPV6_DIP_INDEX 17
/* When a flow offload request comes the following state transitions
* happen based on the order in which the outer & inner flow offload
* requests arrive.
*
* If inner tunnel flow offload request arrives first then the flow
* state will remain in BNXT_ULP_FLOW_STATE_NORMAL state.
* The following outer tunnel flow offload request will change the
* state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from
* BNXT_ULP_FLOW_STATE_NORMAL.
*
* If outer tunnel flow offload request arrives first then the flow state
* will change from BNXT_ULP_FLOW_STATE_NORMAL to
* BNXT_ULP_FLOW_STATE_TUN_O_OFFLD.
*
* Once the flow state is in BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, any inner
* tunnel flow offload requests after that point will be treated as a
* normal flow and the tunnel flow state remains in
* BNXT_ULP_FLOW_STATE_TUN_O_OFFLD
*/
enum bnxt_ulp_tun_flow_state {
BNXT_ULP_FLOW_STATE_NORMAL = 0,
BNXT_ULP_FLOW_STATE_TUN_O_OFFLD,
};
struct ulp_per_port_flow_info {
enum bnxt_ulp_tun_flow_state state;
uint32_t tun_i_cnt;
STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list;
};
struct bnxt_tun_cache_entry {
bool t_dst_ip_valid;
uint8_t t_dmac[RTE_ETHER_ADDR_LEN];
@ -78,17 +23,39 @@ struct bnxt_tun_cache_entry {
uint8_t t_dst_ip6[16];
};
uint32_t outer_tun_flow_id;
uint16_t outer_tun_rej_cnt;
struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS];
};
void
ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl);
struct bnxt_flow_app_tun_ent {
struct rte_flow_tunnel app_tunnel;
uint32_t tun_id;
uint32_t ref_cnt;
struct rte_flow_action action;
struct rte_flow_item item;
};
int32_t
ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx,
struct rte_flow_tunnel *app_tunnel,
struct bnxt_flow_app_tun_ent **tun_entry);
void
ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx);
ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry);
int32_t
ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry);
int32_t
ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry);
struct bnxt_flow_app_tun_ent *
ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx, const void *ctx);
/* Tunnel API to delete the tunnel entry */
void
ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid);
ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
uint8_t tun_idx);
int32_t
ulp_tunnel_offload_process(struct ulp_rte_parser_params *params);
#endif