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igb: add PF support

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Signed-off-by: Intel
This commit is contained in:
Intel 2013-06-03 00:00:00 +00:00 committed by Thomas Monjalon
parent 0f72e563a2
commit be2d648a2d
5 changed files with 610 additions and 26 deletions
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1
lib/librte_pmd_e1000/Makefile
View File

@ -85,6 +85,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_IGB_PMD) += igb_ethdev.c
SRCS-$(CONFIG_RTE_LIBRTE_IGB_PMD) += igb_rxtx.c
SRCS-$(CONFIG_RTE_LIBRTE_EM_PMD) += em_ethdev.c
SRCS-$(CONFIG_RTE_LIBRTE_EM_PMD) += em_rxtx.c
SRCS-$(CONFIG_RTE_LIBRTE_EM_PMD) += igb_pf.c
# this lib depends upon:
DEPDIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += lib/librte_eal lib/librte_ether

29
lib/librte_pmd_e1000/e1000_ethdev.h
View File

@ -37,6 +37,7 @@
/* need update link, bit flag */
#define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
#define E1000_FLAG_MAILBOX (uint32_t)(1 << 1)
/*
* Defines that were not part of e1000_hw.h as they are not used by the FreeBSD
@ -63,6 +64,21 @@ struct e1000_vfta {
uint32_t vfta[IGB_VFTA_SIZE];
};
/*
* VF data which used by PF host only
*/
#define E1000_MAX_VF_MC_ENTRIES 30
struct e1000_vf_info {
uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
uint16_t vf_mc_hashes[E1000_MAX_VF_MC_ENTRIES];
uint16_t num_vf_mc_hashes;
uint16_t default_vf_vlan_id;
uint16_t vlans_enabled;
uint16_t pf_qos;
uint16_t vlan_count;
uint16_t tx_rate;
};
/*
* Structure to store private data for each driver instance (for each port).
*/
@ -71,6 +87,7 @@ struct e1000_adapter {
struct e1000_hw_stats stats;
struct e1000_interrupt intr;
struct e1000_vfta shadow_vfta;
struct e1000_vf_info *vfdata;
};
#define E1000_DEV_PRIVATE_TO_HW(adapter) \
@ -85,6 +102,9 @@ struct e1000_adapter {
#define E1000_DEV_PRIVATE_TO_VFTA(adapter) \
(&((struct e1000_adapter *)adapter)->shadow_vfta)
#define E1000_DEV_PRIVATE_TO_P_VFDATA(adapter) \
(&((struct e1000_adapter *)adapter)->vfdata)
/*
* RX/TX IGB function prototypes
*/
@ -121,6 +141,15 @@ int eth_igbvf_rx_init(struct rte_eth_dev *dev);
void eth_igbvf_tx_init(struct rte_eth_dev *dev);
/*
* misc function prototypes
*/
void igb_pf_host_init(struct rte_eth_dev *eth_dev);
void igb_pf_mbx_process(struct rte_eth_dev *eth_dev);
int igb_pf_host_configure(struct rte_eth_dev *eth_dev);
/*
* RX/TX EM function prototypes
*/

60
lib/librte_pmd_e1000/igb_ethdev.c
View File

@ -139,6 +139,8 @@ static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
#define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
#define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
#define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
/*
@ -284,6 +286,23 @@ igb_intr_disable(struct e1000_hw *hw)
E1000_WRITE_FLUSH(hw);
}
static inline int32_t
igb_pf_reset_hw(struct e1000_hw *hw)
{
uint32_t ctrl_ext;
int32_t status;
status = e1000_reset_hw(hw);
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
/* Set PF Reset Done bit so PF/VF Mail Ops can work */
ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
return status;
}
static void
igb_identify_hardware(struct rte_eth_dev *dev)
{
@ -310,6 +329,7 @@ eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
struct e1000_vfta * shadow_vfta =
E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
uint32_t ctrl_ext;
pci_dev = eth_dev->pci_dev;
eth_dev->dev_ops = &eth_igb_ops;
@ -350,7 +370,7 @@ eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
* Start from a known state, this is important in reading the nvm
* and mac from that.
*/
e1000_reset_hw(hw);
igb_pf_reset_hw(hw);
/* Make sure we have a good EEPROM before we read from it */
if (e1000_validate_nvm_checksum(hw) < 0) {
@ -406,6 +426,15 @@ eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
"SOL/IDER session");
}
/* initialize PF if max_vfs not zero */
igb_pf_host_init(eth_dev);
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
/* Set PF Reset Done bit so PF/VF Mail Ops can work */
ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
eth_dev->data->port_id, pci_dev->id.vendor_id,
pci_dev->id.device_id);
@ -461,7 +490,7 @@ eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
/* Disable the interrupts for VF */
igbvf_intr_disable(hw);
diag = hw->mac.ops.reset_hw(hw);
/* Allocate memory for storing MAC addresses */
@ -474,6 +503,7 @@ eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
ETHER_ADDR_LEN * hw->mac.rar_entry_count);
return -ENOMEM;
}
/* Copy the permanent MAC address */
ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
&eth_dev->data->mac_addrs[0]);
@ -556,6 +586,7 @@ eth_igb_start(struct rte_eth_dev *dev)
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
int ret, i, mask;
uint32_t ctrl_ext;
PMD_INIT_LOG(DEBUG, ">>");
@ -585,6 +616,15 @@ eth_igb_start(struct rte_eth_dev *dev)
E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
/* Set PF Reset Done bit so PF/VF Mail Ops can work */
ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
/* configure PF module if SRIOV enabled */
igb_pf_host_configure(dev);
/* Configure for OS presence */
igb_init_manageability(hw);
@ -714,7 +754,7 @@ eth_igb_stop(struct rte_eth_dev *dev)
struct rte_eth_link link;
igb_intr_disable(hw);
e1000_reset_hw(hw);
igb_pf_reset_hw(hw);
E1000_WRITE_REG(hw, E1000_WUC, 0);
/* Power down the phy. Needed to make the link go Down */
@ -806,7 +846,7 @@ igb_hardware_init(struct e1000_hw *hw)
hw->fc.requested_mode = e1000_fc_none;
/* Issue a global reset */
e1000_reset_hw(hw);
igb_pf_reset_hw(hw);
E1000_WRITE_REG(hw, E1000_WUC, 0);
diag = e1000_init_hw(hw);
@ -1493,6 +1533,9 @@ eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
}
if (icr & E1000_ICR_VMMB)
intr->flags |= E1000_FLAG_MAILBOX;
return 0;
}
@ -1517,6 +1560,10 @@ eth_igb_interrupt_action(struct rte_eth_dev *dev)
struct rte_eth_link link;
int ret;
if (intr->flags & E1000_FLAG_MAILBOX) {
igb_pf_mbx_process(dev);
intr->flags &= ~E1000_FLAG_MAILBOX;
}
igb_intr_enable(dev);
rte_intr_enable(&(dev->pci_dev->intr_handle));
@ -1650,13 +1697,18 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
return (-EIO);
}
#define E1000_RAH_POOLSEL_SHIFT (18)
static void
eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
uint32_t index, __rte_unused uint32_t pool)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t rah;
e1000_rar_set(hw, mac_addr->addr_bytes, index);
rah = E1000_READ_REG(hw, E1000_RAH(index));
rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
E1000_WRITE_REG(hw, E1000_RAH(index), rah);
}
static void

494
lib/librte_pmd_e1000/igb_pf.c Normal file
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@ -0,0 +1,494 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include <errno.h>
#include <stdint.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdarg.h>
#include <inttypes.h>
#include <rte_interrupts.h>
#include <rte_log.h>
#include <rte_debug.h>
#include <rte_eal.h>
#include <rte_ether.h>
#include <rte_ethdev.h>
#include <rte_memcpy.h>
#include <rte_malloc.h>
#include <rte_random.h>
#include "e1000/e1000_defines.h"
#include "e1000/e1000_regs.h"
#include "e1000/e1000_hw.h"
#include "e1000_ethdev.h"
static inline
void eth_random_addr(uint8_t *addr)
{
uint64_t rand = rte_rand();
uint8_t *p = (uint8_t*)&rand;
rte_memcpy(addr, p, ETHER_ADDR_LEN);
addr[0] &= 0xfe; /* clear multicast bit */
addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
}
static inline uint16_t
dev_num_vf(struct rte_eth_dev *eth_dev)
{
return eth_dev->pci_dev->max_vfs;
}
static inline
int igb_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
{
unsigned char vf_mac_addr[ETHER_ADDR_LEN];
struct e1000_vf_info *vfinfo =
*E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
uint16_t vfn;
for (vfn = 0; vfn < vf_num; vfn++) {
eth_random_addr(vf_mac_addr);
/* keep the random address as default */
memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
ETHER_ADDR_LEN);
}
return 0;
}
static inline int
igb_mb_intr_setup(struct rte_eth_dev *dev)
{
struct e1000_interrupt *intr =
E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
intr->mask |= E1000_ICR_VMMB;
return 0;
}
void igb_pf_host_init(struct rte_eth_dev *eth_dev)
{
struct e1000_vf_info **vfinfo =
E1000_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
uint16_t vf_num;
uint8_t nb_queue;
RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
if (0 == (vf_num = dev_num_vf(eth_dev)))
return;
if (hw->mac.type == e1000_i350)
nb_queue = 1;
else if(hw->mac.type == e1000_82576)
/* per datasheet, it should be 2, but 1 seems correct */
nb_queue = 1;
else
return;
*vfinfo = rte_zmalloc("vf_info", sizeof(struct e1000_vf_info) * vf_num, 0);
if (*vfinfo == NULL)
rte_panic("Cannot allocate memory for private VF data\n");
RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_8_POOLS;
RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
igb_vf_perm_addr_gen(eth_dev, vf_num);
/* set mb interrupt mask */
igb_mb_intr_setup(eth_dev);
return;
}
#define E1000_RAH_POOLSEL_SHIFT (18)
int igb_pf_host_configure(struct rte_eth_dev *eth_dev)
{
uint32_t vtctl;
uint16_t vf_num;
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
uint32_t vlanctrl;
int i;
uint32_t rah;
if (0 == (vf_num = dev_num_vf(eth_dev)))
return -1;
/* enable VMDq and set the default pool for PF */
vtctl = E1000_READ_REG(hw, E1000_VT_CTL);
vtctl &= ~E1000_VT_CTL_DEFAULT_POOL_MASK;
vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
<< E1000_VT_CTL_DEFAULT_POOL_SHIFT;
vtctl |= E1000_VT_CTL_VM_REPL_EN;
E1000_WRITE_REG(hw, E1000_VT_CTL, vtctl);
/* Enable pools reserved to PF only */
E1000_WRITE_REG(hw, E1000_VFRE, (~0) << vf_num);
E1000_WRITE_REG(hw, E1000_VFTE, (~0) << vf_num);
/* PFDMA Tx General Switch Control Enables VMDQ loopback */
if (hw->mac.type == e1000_i350)
E1000_WRITE_REG(hw, E1000_TXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
else
E1000_WRITE_REG(hw, E1000_DTXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
/* clear VMDq map to perment rar 0 */
rah = E1000_READ_REG(hw, E1000_RAH(0));
rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
E1000_WRITE_REG(hw, E1000_RAH(0), rah);
/* clear VMDq map to scan rar 32 */
rah = E1000_READ_REG(hw, E1000_RAH(hw->mac.rar_entry_count));
rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
E1000_WRITE_REG(hw, E1000_RAH(hw->mac.rar_entry_count), rah);
/* set VMDq map to default PF pool */
rah = E1000_READ_REG(hw, E1000_RAH(0));
rah |= (0x1 << (RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx +
E1000_RAH_POOLSEL_SHIFT));
E1000_WRITE_REG(hw, E1000_RAH(0), rah);
/*
* enable vlan filtering and allow all vlan tags through
*/
vlanctrl = E1000_READ_REG(hw, E1000_RCTL);
vlanctrl |= E1000_RCTL_VFE ; /* enable vlan filters */
E1000_WRITE_REG(hw, E1000_RCTL, vlanctrl);
/* VFTA - enable all vlan filters */
for (i = 0; i < IGB_VFTA_SIZE; i++) {
E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, 0xFFFFFFFF);
}
/* Enable/Disable MAC Anti-Spoofing */
e1000_vmdq_set_anti_spoofing_pf(hw, FALSE, vf_num);
return 0;
}
static void
set_rx_mode(struct rte_eth_dev *dev)
{
struct rte_eth_dev_data *dev_data =
(struct rte_eth_dev_data*)dev->data->dev_private;
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t fctrl, vmolr = E1000_VMOLR_BAM | E1000_VMOLR_AUPE;
uint16_t vfn = dev_num_vf(dev);
/* Check for Promiscuous and All Multicast modes */
fctrl = E1000_READ_REG(hw, E1000_RCTL);
/* set all bits that we expect to always be set */
fctrl &= ~E1000_RCTL_SBP; /* disable store-bad-packets */
fctrl |= E1000_RCTL_BAM;;
/* clear the bits we are changing the status of */
fctrl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
if (dev_data->promiscuous) {
fctrl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
} else {
if (dev_data->all_multicast) {
fctrl |= E1000_RCTL_MPE;
vmolr |= E1000_VMOLR_MPME;
} else {
vmolr |= E1000_VMOLR_ROMPE;
}
}
if ((hw->mac.type == e1000_82576) ||
(hw->mac.type == e1000_i350)) {
vmolr |= E1000_READ_REG(hw, E1000_VMOLR(vfn)) &
~(E1000_VMOLR_MPME | E1000_VMOLR_ROMPE |
E1000_VMOLR_ROPE);
E1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);
}
E1000_WRITE_REG(hw, E1000_RCTL, fctrl);
}
static inline void
igb_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
{
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct e1000_vf_info *vfinfo =
*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
uint32_t vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));
vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE |
E1000_VMOLR_BAM | E1000_VMOLR_AUPE);
E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);
E1000_WRITE_REG(hw, E1000_VMVIR(vf), 0);
/* reset multicast table array for vf */
vfinfo[vf].num_vf_mc_hashes = 0;
/* reset rx mode */
set_rx_mode(dev);
}
static inline void
igb_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t reg;
/* enable transmit and receive for vf */
reg = E1000_READ_REG(hw, E1000_VFTE);
reg |= (reg | (1 << vf));
E1000_WRITE_REG(hw, E1000_VFTE, reg);
reg = E1000_READ_REG(hw, E1000_VFRE);
reg |= (reg | (1 << vf));
E1000_WRITE_REG(hw, E1000_VFRE, reg);
igb_vf_reset_event(dev, vf);
}
static int
igb_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct e1000_vf_info *vfinfo =
*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
int rar_entry = hw->mac.rar_entry_count - (vf + 1);
uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
uint32_t rah;
igb_vf_reset_msg(dev, vf);
hw->mac.ops.rar_set(hw, vf_mac, rar_entry);
rah = E1000_READ_REG(hw, E1000_RAH(rar_entry));
rah |= (0x1 << (vf + E1000_RAH_POOLSEL_SHIFT));
E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah);
/* reply to reset with ack and vf mac address */
msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
e1000_write_mbx(hw, msgbuf, 3, vf);
return 0;
}
static int
igb_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct e1000_vf_info *vfinfo =
*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
int rar_entry = hw->mac.rar_entry_count - (vf + 1);
uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
hw->mac.ops.rar_set(hw, new_mac, rar_entry);
return 0;
}
return -1;
}
static int
igb_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
{
int i;
uint32_t vector_bit;
uint32_t vector_reg;
uint32_t mta_reg;
int entries = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >>
E1000_VT_MSGINFO_SHIFT;
uint16_t *hash_list = (uint16_t *)&msgbuf[1];
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct e1000_vf_info *vfinfo =
*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
/* only so many hash values supported */
entries = RTE_MIN(entries, E1000_MAX_VF_MC_ENTRIES);
/*
* salt away the number of multi cast addresses assigned
* to this VF for later use to restore when the PF multi cast
* list changes
*/
vfinfo->num_vf_mc_hashes = (uint16_t)entries;
/*
* VFs are limited to using the MTA hash table for their multicast
* addresses
*/
for (i = 0; i < entries; i++) {
vfinfo->vf_mc_hashes[i] = hash_list[i];
}
for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
vector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F;
vector_bit = vfinfo->vf_mc_hashes[i] & 0x1F;
mta_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, vector_reg);
mta_reg |= (1 << vector_bit);
E1000_WRITE_REG_ARRAY(hw, E1000_MTA, vector_reg, mta_reg);
}
return 0;
}
static int
igb_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
{
int add, vid;
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct e1000_vf_info *vfinfo =
*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
uint32_t vid_idx, vid_bit, vfta;
add = (msgbuf[0] & E1000_VT_MSGINFO_MASK)
>> E1000_VT_MSGINFO_SHIFT;
vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
if (add)
vfinfo[vf].vlan_count++;
else if (vfinfo[vf].vlan_count)
vfinfo[vf].vlan_count--;
vid_idx = (uint32_t)((vid >> E1000_VFTA_ENTRY_SHIFT) &
E1000_VFTA_ENTRY_MASK);
vid_bit = (uint32_t)(1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
if (add)
vfta |= vid_bit;
else
vfta &= ~vid_bit;
E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
E1000_WRITE_FLUSH(hw);
return 0;
}
static int
igb_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
{
uint16_t mbx_size = E1000_VFMAILBOX_SIZE;
uint32_t msgbuf[E1000_VFMAILBOX_SIZE];
int32_t retval;
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
retval = e1000_read_mbx(hw, msgbuf, mbx_size, vf);
if (retval) {
RTE_LOG(ERR, PMD, "Error mbx recv msg from VF %d\n", vf);
return retval;
}
/* do nothing with the message already processed */
if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
return retval;
/* flush the ack before we write any messages back */
E1000_WRITE_FLUSH(hw);
/* perform VF reset */
if (msgbuf[0] == E1000_VF_RESET) {
return igb_vf_reset(dev, vf, msgbuf);
}
/* check & process VF to PF mailbox message */
switch ((msgbuf[0] & 0xFFFF)) {
case E1000_VF_SET_MAC_ADDR:
retval = igb_vf_set_mac_addr(dev, vf, msgbuf);
break;
case E1000_VF_SET_MULTICAST:
retval = igb_vf_set_multicast(dev, vf, msgbuf);
break;
case E1000_VF_SET_VLAN:
retval = igb_vf_set_vlan(dev, vf, msgbuf);
break;
default:
RTE_LOG(DEBUG, PMD, "Unhandled Msg %8.8x\n", (unsigned) msgbuf[0]);
retval = E1000_ERR_MBX;
break;
}
/* response the VF according to the message process result */
if (retval)
msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
else
msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
e1000_write_mbx(hw, msgbuf, 1, vf);
return retval;
}
static inline void
igb_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
{
uint32_t msg = E1000_VT_MSGTYPE_NACK;
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
e1000_write_mbx(hw, &msg, 1, vf);
}
void igb_pf_mbx_process(struct rte_eth_dev *eth_dev)
{
uint16_t vf;
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
/* check & process vf function level reset */
if (!e1000_check_for_rst(hw, vf))
igb_vf_reset_event(eth_dev, vf);
/* check & process vf mailbox messages */
if (!e1000_check_for_msg(hw, vf))
igb_rcv_msg_from_vf(eth_dev, vf);
/* check & process acks from vf */
if (!e1000_check_for_ack(hw, vf))
igb_rcv_ack_from_vf(eth_dev, vf);
}
}

52
lib/librte_pmd_e1000/igb_rxtx.c
View File

@ -126,6 +126,7 @@ struct igb_rx_queue {
uint16_t nb_rx_hold; /**< number of held free RX desc. */
uint16_t rx_free_thresh; /**< max free RX desc to hold. */
uint16_t queue_id; /**< RX queue index. */
uint16_t reg_idx; /**< RX queue register index. */
uint8_t port_id; /**< Device port identifier. */
uint8_t pthresh; /**< Prefetch threshold register. */
uint8_t hthresh; /**< Host threshold register. */
@ -166,6 +167,7 @@ struct igb_tx_queue {
uint16_t tx_head;
/**< Index of first used TX descriptor. */
uint16_t queue_id; /**< TX queue index. */
uint16_t reg_idx; /**< TX queue register index. */
uint8_t port_id; /**< Device port identifier. */
uint8_t pthresh; /**< Prefetch threshold register. */
uint8_t hthresh; /**< Host threshold register. */
@ -1229,9 +1231,11 @@ eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
txq->hthresh = tx_conf->tx_thresh.hthresh;
txq->wthresh = tx_conf->tx_thresh.wthresh;
txq->queue_id = queue_idx;
txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
txq->port_id = dev->data->port_id;
txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));
txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
@ -1345,6 +1349,8 @@ eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
rxq->drop_en = rx_conf->rx_drop_en;
rxq->rx_free_thresh = rx_conf->rx_free_thresh;
rxq->queue_id = queue_idx;
rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
rxq->port_id = dev->data->port_id;
rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
ETHER_CRC_LEN);
@ -1360,8 +1366,8 @@ eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
igb_rx_queue_release(rxq);
return (-ENOMEM);
}
rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));
rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(queue_idx));
rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
@ -1641,12 +1647,12 @@ eth_igb_rx_init(struct rte_eth_dev *dev)
0 : ETHER_CRC_LEN);
bus_addr = rxq->rx_ring_phys_addr;
E1000_WRITE_REG(hw, E1000_RDLEN(i),
E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
rxq->nb_rx_desc *
sizeof(union e1000_adv_rx_desc));
E1000_WRITE_REG(hw, E1000_RDBAH(i),
E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
(uint32_t)(bus_addr >> 32));
E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
@ -1691,16 +1697,16 @@ eth_igb_rx_init(struct rte_eth_dev *dev)
if (rxq->drop_en)
srrctl |= E1000_SRRCTL_DROP_EN;
E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
/* Enable this RX queue. */
rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
rxdctl &= 0xFFF00000;
rxdctl |= (rxq->pthresh & 0x1F);
rxdctl |= ((rxq->hthresh & 0x1F) << 8);
rxdctl |= ((rxq->wthresh & 0x1F) << 16);
E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
}
/*
@ -1753,10 +1759,11 @@ eth_igb_rx_init(struct rte_eth_dev *dev)
/* set STRCRC bit in all queues for Powerville/Springville */
if (hw->mac.type == e1000_i350 || hw->mac.type == e1000_i210) {
for (i = 0; i < dev->data->nb_rx_queues; i++) {
rxq = dev->data->rx_queues[i];
uint32_t dvmolr = E1000_READ_REG(hw,
E1000_DVMOLR(i));
E1000_DVMOLR(rxq->reg_idx));
dvmolr |= E1000_DVMOLR_STRCRC;
E1000_WRITE_REG(hw, E1000_DVMOLR(i), dvmolr);
E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
}
}
} else {
@ -1765,10 +1772,11 @@ eth_igb_rx_init(struct rte_eth_dev *dev)
/* clear STRCRC bit in all queues for Powerville/Springville */
if (hw->mac.type == e1000_i350 || hw->mac.type == e1000_i210) {
for (i = 0; i < dev->data->nb_rx_queues; i++) {
rxq = dev->data->rx_queues[i];
uint32_t dvmolr = E1000_READ_REG(hw,
E1000_DVMOLR(i));
E1000_DVMOLR(rxq->reg_idx));
dvmolr &= ~E1000_DVMOLR_STRCRC;
E1000_WRITE_REG(hw, E1000_DVMOLR(i), dvmolr);
E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
}
}
}
@ -1792,8 +1800,8 @@ eth_igb_rx_init(struct rte_eth_dev *dev)
*/
for (i = 0; i < dev->data->nb_rx_queues; i++) {
rxq = dev->data->rx_queues[i];
E1000_WRITE_REG(hw, E1000_RDH(i), 0);
E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
}
return 0;
@ -1821,24 +1829,24 @@ eth_igb_tx_init(struct rte_eth_dev *dev)
txq = dev->data->tx_queues[i];
bus_addr = txq->tx_ring_phys_addr;
E1000_WRITE_REG(hw, E1000_TDLEN(i),
E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
txq->nb_tx_desc *
sizeof(union e1000_adv_tx_desc));
E1000_WRITE_REG(hw, E1000_TDBAH(i),
E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
(uint32_t)(bus_addr >> 32));
E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
/* Setup the HW Tx Head and Tail descriptor pointers. */
E1000_WRITE_REG(hw, E1000_TDT(i), 0);
E1000_WRITE_REG(hw, E1000_TDH(i), 0);
E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
/* Setup Transmit threshold registers. */
txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
txdctl |= txq->pthresh & 0x1F;
txdctl |= ((txq->hthresh & 0x1F) << 8);
txdctl |= ((txq->wthresh & 0x1F) << 16);
txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
}
/* Program the Transmit Control Register. */