baseband/acc200: add LTE processing
Added functions and capability for 4G FEC Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
This commit is contained in:
Nicolas Chautru
Akhil Goyal
parent
e640f6cdfa
commit
bec597b78a
@ -650,6 +650,46 @@ acc200_dev_info_get(struct rte_bbdev *dev,
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struct acc_device *d = dev->data->dev_private;
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int i;
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static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
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{
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.type = RTE_BBDEV_OP_TURBO_DEC,
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.cap.turbo_dec = {
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.capability_flags =
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RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE |
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RTE_BBDEV_TURBO_CRC_TYPE_24B |
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RTE_BBDEV_TURBO_EQUALIZER |
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RTE_BBDEV_TURBO_SOFT_OUT_SATURATE |
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RTE_BBDEV_TURBO_HALF_ITERATION_EVEN |
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RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH |
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RTE_BBDEV_TURBO_SOFT_OUTPUT |
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RTE_BBDEV_TURBO_EARLY_TERMINATION |
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RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN |
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RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT |
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RTE_BBDEV_TURBO_MAP_DEC |
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RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP |
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RTE_BBDEV_TURBO_DEC_SCATTER_GATHER,
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.max_llr_modulus = INT8_MAX,
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.num_buffers_src =
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RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
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.num_buffers_hard_out =
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RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
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.num_buffers_soft_out =
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RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
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}
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},
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{
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.type = RTE_BBDEV_OP_TURBO_ENC,
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.cap.turbo_enc = {
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.capability_flags =
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RTE_BBDEV_TURBO_CRC_24B_ATTACH |
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RTE_BBDEV_TURBO_RV_INDEX_BYPASS |
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RTE_BBDEV_TURBO_RATE_MATCH |
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RTE_BBDEV_TURBO_ENC_SCATTER_GATHER,
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.num_buffers_src =
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RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
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.num_buffers_dst =
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RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
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}
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},
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{
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.type = RTE_BBDEV_OP_LDPC_ENC,
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.cap.ldpc_enc = {
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@ -701,15 +741,17 @@ acc200_dev_info_get(struct rte_bbdev *dev,
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/* Exposed number of queues. */
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dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0;
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dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = 0;
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dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = 0;
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dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = d->acc_conf.q_ul_4g.num_aqs_per_groups *
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d->acc_conf.q_ul_4g.num_qgroups;
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dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = d->acc_conf.q_dl_4g.num_aqs_per_groups *
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d->acc_conf.q_dl_4g.num_qgroups;
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dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = d->acc_conf.q_ul_5g.num_aqs_per_groups *
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d->acc_conf.q_ul_5g.num_qgroups;
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dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = d->acc_conf.q_dl_5g.num_aqs_per_groups *
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d->acc_conf.q_dl_5g.num_qgroups;
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dev_info->num_queues[RTE_BBDEV_OP_FFT] = 0;
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dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = 0;
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dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = 0;
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dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = d->acc_conf.q_ul_4g.num_qgroups;
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dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = d->acc_conf.q_dl_4g.num_qgroups;
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dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = d->acc_conf.q_ul_5g.num_qgroups;
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dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = d->acc_conf.q_dl_5g.num_qgroups;
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dev_info->queue_priority[RTE_BBDEV_OP_FFT] = 0;
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@ -754,6 +796,70 @@ static struct rte_pci_id pci_id_acc200_vf_map[] = {
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{.device_id = 0},
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};
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/* Fill in a frame control word for turbo decoding. */
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static inline void
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acc200_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc_fcw_td *fcw)
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{
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fcw->fcw_ver = 1;
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fcw->num_maps = ACC_FCW_TD_AUTOMAP;
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fcw->bypass_sb_deint = !check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE);
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if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) {
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/* FIXME for TB block */
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fcw->k_pos = op->turbo_dec.tb_params.k_pos;
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fcw->k_neg = op->turbo_dec.tb_params.k_neg;
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} else {
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fcw->k_pos = op->turbo_dec.cb_params.k;
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fcw->k_neg = op->turbo_dec.cb_params.k;
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}
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fcw->c = 1;
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fcw->c_neg = 1;
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if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
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fcw->soft_output_en = 1;
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fcw->sw_soft_out_dis = 0;
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fcw->sw_et_cont = check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH);
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fcw->sw_soft_out_saturation = check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_SOFT_OUT_SATURATE);
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if (check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_EQUALIZER)) {
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fcw->bypass_teq = 0;
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fcw->ea = op->turbo_dec.cb_params.e;
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fcw->eb = op->turbo_dec.cb_params.e;
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if (op->turbo_dec.rv_index == 0)
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fcw->k0_start_col = ACC_FCW_TD_RVIDX_0;
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else if (op->turbo_dec.rv_index == 1)
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fcw->k0_start_col = ACC_FCW_TD_RVIDX_1;
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else if (op->turbo_dec.rv_index == 2)
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fcw->k0_start_col = ACC_FCW_TD_RVIDX_2;
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else
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fcw->k0_start_col = ACC_FCW_TD_RVIDX_3;
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} else {
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fcw->bypass_teq = 1;
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fcw->eb = 64; /* avoid undefined value */
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}
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} else {
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fcw->soft_output_en = 0;
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fcw->sw_soft_out_dis = 1;
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fcw->bypass_teq = 0;
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}
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fcw->code_block_mode = 1; /* FIXME */
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fcw->turbo_crc_type = check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_CRC_TYPE_24B);
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fcw->ext_td_cold_reg_en = 1;
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fcw->raw_decoder_input_on = 0;
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fcw->max_iter = RTE_MAX((uint8_t) op->turbo_dec.iter_max, 2);
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fcw->min_iter = 2;
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fcw->half_iter_on = !check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
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fcw->early_stop_en = check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_EARLY_TERMINATION) & !fcw->soft_output_en;
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fcw->ext_scale = 0xF;
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}
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/* Fill in a frame control word for LDPC decoding. */
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static inline void
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acc200_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
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@ -877,7 +983,124 @@ acc200_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
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}
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static inline int
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acc200_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, struct acc_dma_req_desc *desc,
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acc200_dma_desc_td_fill(struct rte_bbdev_dec_op *op,
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struct acc_dma_req_desc *desc, struct rte_mbuf **input,
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struct rte_mbuf *h_output, struct rte_mbuf *s_output,
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uint32_t *in_offset, uint32_t *h_out_offset,
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uint32_t *s_out_offset, uint32_t *h_out_length,
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uint32_t *s_out_length, uint32_t *mbuf_total_left,
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uint32_t *seg_total_left, uint8_t r)
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{
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int next_triplet = 1; /* FCW already done. */
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uint16_t k;
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uint16_t crc24_overlap = 0;
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uint32_t e, kw;
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desc->word0 = ACC_DMA_DESC_TYPE;
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desc->word1 = 0; /**< Timestamp could be disabled. */
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desc->word2 = 0;
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desc->word3 = 0;
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desc->numCBs = 1;
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if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) {
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k = (r < op->turbo_dec.tb_params.c_neg)
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? op->turbo_dec.tb_params.k_neg
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: op->turbo_dec.tb_params.k_pos;
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e = (r < op->turbo_dec.tb_params.cab)
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? op->turbo_dec.tb_params.ea
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: op->turbo_dec.tb_params.eb;
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} else {
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k = op->turbo_dec.cb_params.k;
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e = op->turbo_dec.cb_params.e;
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}
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if ((op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
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&& !check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP))
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crc24_overlap = 24;
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/* Calculates circular buffer size.
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* According to 3gpp 36.212 section 5.1.4.2
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* Kw = 3 * Kpi,
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* where:
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* Kpi = nCol * nRow
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* where nCol is 32 and nRow can be calculated from:
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* D =< nCol * nRow
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* where D is the size of each output from turbo encoder block (k + 4).
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*/
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kw = RTE_ALIGN_CEIL(k + 4, 32) * 3;
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if (unlikely((*mbuf_total_left == 0) || (*mbuf_total_left < kw))) {
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rte_bbdev_log(ERR,
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"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
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*mbuf_total_left, kw);
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return -1;
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}
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next_triplet = acc_dma_fill_blk_type_in(desc, input, in_offset, kw,
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seg_total_left, next_triplet,
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check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_DEC_SCATTER_GATHER));
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if (unlikely(next_triplet < 0)) {
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rte_bbdev_log(ERR,
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"Mismatch between data to process and mbuf data length in bbdev_op: %p",
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op);
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return -1;
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}
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desc->data_ptrs[next_triplet - 1].last = 1;
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desc->m2dlen = next_triplet;
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*mbuf_total_left -= kw;
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*h_out_length = ((k - crc24_overlap) >> 3);
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next_triplet = acc_dma_fill_blk_type(
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desc, h_output, *h_out_offset,
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*h_out_length, next_triplet, ACC_DMA_BLKID_OUT_HARD);
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if (unlikely(next_triplet < 0)) {
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rte_bbdev_log(ERR,
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"Mismatch between data to process and mbuf data length in bbdev_op: %p",
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op);
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return -1;
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}
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op->turbo_dec.hard_output.length += *h_out_length;
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*h_out_offset += *h_out_length;
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/* Soft output. */
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if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
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if (op->turbo_dec.soft_output.data == 0) {
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rte_bbdev_log(ERR, "Soft output is not defined");
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return -1;
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}
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if (check_bit(op->turbo_dec.op_flags,
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RTE_BBDEV_TURBO_EQUALIZER))
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*s_out_length = e;
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else
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*s_out_length = (k * 3) + 12;
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next_triplet = acc_dma_fill_blk_type(desc, s_output,
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*s_out_offset, *s_out_length, next_triplet,
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ACC_DMA_BLKID_OUT_SOFT);
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if (unlikely(next_triplet < 0)) {
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rte_bbdev_log(ERR,
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"Mismatch between data to process and mbuf data length in bbdev_op: %p",
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op);
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return -1;
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}
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op->turbo_dec.soft_output.length += *s_out_length;
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*s_out_offset += *s_out_length;
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}
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desc->data_ptrs[next_triplet - 1].last = 1;
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desc->d2mlen = next_triplet - desc->m2dlen;
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desc->op_addr = op;
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return 0;
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}
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static inline int
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acc200_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,
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struct acc_dma_req_desc *desc,
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struct rte_mbuf **input, struct rte_mbuf *h_output,
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uint32_t *in_offset, uint32_t *h_out_offset,
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uint32_t *h_out_length, uint32_t *mbuf_total_left,
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@ -1035,6 +1258,47 @@ acc200_dma_desc_ld_update(struct rte_bbdev_dec_op *op,
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desc->op_addr = op;
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}
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/* Enqueue one encode operations for ACC200 device in CB mode */
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static inline int
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enqueue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op,
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uint16_t total_enqueued_cbs)
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{
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union acc_dma_desc *desc = NULL;
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int ret;
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uint32_t in_offset, out_offset, out_length, mbuf_total_left, seg_total_left;
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struct rte_mbuf *input, *output_head, *output;
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uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs)
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& q->sw_ring_wrap_mask);
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desc = q->ring_addr + desc_idx;
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acc_fcw_te_fill(op, &desc->req.fcw_te);
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input = op->turbo_enc.input.data;
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output_head = output = op->turbo_enc.output.data;
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in_offset = op->turbo_enc.input.offset;
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out_offset = op->turbo_enc.output.offset;
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out_length = 0;
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mbuf_total_left = op->turbo_enc.input.length;
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seg_total_left = rte_pktmbuf_data_len(op->turbo_enc.input.data) - in_offset;
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ret = acc_dma_desc_te_fill(op, &desc->req, &input, output,
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&in_offset, &out_offset, &out_length, &mbuf_total_left,
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&seg_total_left, 0);
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if (unlikely(ret < 0))
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return ret;
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mbuf_append(output_head, output, out_length);
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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rte_memdump(stderr, "FCW", &desc->req.fcw_te,
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sizeof(desc->req.fcw_te) - 8);
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rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc));
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#endif
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/* One CB (one op) was successfully prepared to enqueue */
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return 1;
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}
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/* Enqueue one encode operations for ACC200 device in CB mode
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* multiplexed on the same descriptor.
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*/
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@ -1147,6 +1411,78 @@ enqueue_ldpc_enc_part_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op,
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}
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/* Enqueue one encode operations for ACC200 device in TB mode. */
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static inline int
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enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op,
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uint16_t total_enqueued_cbs, uint8_t cbs_in_tb)
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{
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union acc_dma_desc *desc = NULL;
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int ret;
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uint8_t r, c;
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uint32_t in_offset, out_offset, out_length, mbuf_total_left,
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seg_total_left;
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struct rte_mbuf *input, *output_head, *output;
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uint16_t current_enqueued_cbs = 0;
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uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs)
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& q->sw_ring_wrap_mask);
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desc = q->ring_addr + desc_idx;
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uint64_t fcw_offset = (desc_idx << 8) + ACC_DESC_FCW_OFFSET;
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acc_fcw_te_fill(op, &desc->req.fcw_te);
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input = op->turbo_enc.input.data;
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output_head = output = op->turbo_enc.output.data;
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in_offset = op->turbo_enc.input.offset;
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out_offset = op->turbo_enc.output.offset;
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out_length = 0;
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mbuf_total_left = op->turbo_enc.input.length;
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c = op->turbo_enc.tb_params.c;
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r = op->turbo_enc.tb_params.r;
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while (mbuf_total_left > 0 && r < c) {
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seg_total_left = rte_pktmbuf_data_len(input) - in_offset;
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/* Set up DMA descriptor */
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desc = q->ring_addr + ((q->sw_ring_head + total_enqueued_cbs)
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& q->sw_ring_wrap_mask);
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desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset;
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desc->req.data_ptrs[0].blen = ACC_FCW_TE_BLEN;
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ret = acc_dma_desc_te_fill(op, &desc->req, &input, output,
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&in_offset, &out_offset, &out_length,
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&mbuf_total_left, &seg_total_left, r);
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if (unlikely(ret < 0))
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return ret;
|
||||
mbuf_append(output_head, output, out_length);
|
||||
|
||||
/* Set total number of CBs in TB */
|
||||
desc->req.cbs_in_tb = cbs_in_tb;
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
rte_memdump(stderr, "FCW", &desc->req.fcw_te,
|
||||
sizeof(desc->req.fcw_te) - 8);
|
||||
rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc));
|
||||
#endif
|
||||
|
||||
if (seg_total_left == 0) {
|
||||
/* Go to the next mbuf */
|
||||
input = input->next;
|
||||
in_offset = 0;
|
||||
output = output->next;
|
||||
out_offset = 0;
|
||||
}
|
||||
|
||||
total_enqueued_cbs++;
|
||||
current_enqueued_cbs++;
|
||||
r++;
|
||||
}
|
||||
|
||||
/* Set SDone on last CB descriptor for TB mode. */
|
||||
desc->req.sdone_enable = 1;
|
||||
desc->req.irq_enable = q->irq_enable;
|
||||
|
||||
return current_enqueued_cbs;
|
||||
}
|
||||
|
||||
/* Enqueue one encode operations for ACC200 device in TB mode.
|
||||
* returns the number of descs used.
|
||||
*/
|
||||
@ -1214,6 +1550,62 @@ enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op,
|
||||
|
||||
/** Enqueue one decode operations for ACC200 device in CB mode. */
|
||||
static inline int
|
||||
enqueue_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,
|
||||
uint16_t total_enqueued_cbs)
|
||||
{
|
||||
union acc_dma_desc *desc = NULL;
|
||||
int ret;
|
||||
uint32_t in_offset, h_out_offset, s_out_offset, s_out_length,
|
||||
h_out_length, mbuf_total_left, seg_total_left;
|
||||
struct rte_mbuf *input, *h_output_head, *h_output,
|
||||
*s_output_head, *s_output;
|
||||
|
||||
uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs)
|
||||
& q->sw_ring_wrap_mask);
|
||||
desc = q->ring_addr + desc_idx;
|
||||
acc200_fcw_td_fill(op, &desc->req.fcw_td);
|
||||
|
||||
input = op->turbo_dec.input.data;
|
||||
h_output_head = h_output = op->turbo_dec.hard_output.data;
|
||||
s_output_head = s_output = op->turbo_dec.soft_output.data;
|
||||
in_offset = op->turbo_dec.input.offset;
|
||||
h_out_offset = op->turbo_dec.hard_output.offset;
|
||||
s_out_offset = op->turbo_dec.soft_output.offset;
|
||||
h_out_length = s_out_length = 0;
|
||||
mbuf_total_left = op->turbo_dec.input.length;
|
||||
seg_total_left = rte_pktmbuf_data_len(input) - in_offset;
|
||||
|
||||
/* Set up DMA descriptor */
|
||||
desc = q->ring_addr + ((q->sw_ring_head + total_enqueued_cbs)
|
||||
& q->sw_ring_wrap_mask);
|
||||
|
||||
ret = acc200_dma_desc_td_fill(op, &desc->req, &input, h_output,
|
||||
s_output, &in_offset, &h_out_offset, &s_out_offset,
|
||||
&h_out_length, &s_out_length, &mbuf_total_left,
|
||||
&seg_total_left, 0);
|
||||
|
||||
if (unlikely(ret < 0))
|
||||
return ret;
|
||||
|
||||
/* Hard output */
|
||||
mbuf_append(h_output_head, h_output, h_out_length);
|
||||
|
||||
/* Soft output */
|
||||
if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT))
|
||||
mbuf_append(s_output_head, s_output, s_out_length);
|
||||
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
rte_memdump(stderr, "FCW", &desc->req.fcw_td,
|
||||
sizeof(desc->req.fcw_td));
|
||||
rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc));
|
||||
#endif
|
||||
|
||||
/* One CB (one op) was successfully prepared to enqueue */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/** Enqueue one decode operations for ACC200 device in CB mode */
|
||||
static inline int
|
||||
enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,
|
||||
uint16_t total_enqueued_cbs, bool same_op)
|
||||
{
|
||||
@ -1396,6 +1788,139 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,
|
||||
return current_enqueued_cbs;
|
||||
}
|
||||
|
||||
/* Enqueue one decode operations for ACC200 device in TB mode */
|
||||
static inline int
|
||||
enqueue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,
|
||||
uint16_t total_enqueued_cbs, uint8_t cbs_in_tb)
|
||||
{
|
||||
union acc_dma_desc *desc = NULL;
|
||||
int ret;
|
||||
uint8_t r, c;
|
||||
uint32_t in_offset, h_out_offset, s_out_offset, s_out_length,
|
||||
h_out_length, mbuf_total_left, seg_total_left;
|
||||
struct rte_mbuf *input, *h_output_head, *h_output,
|
||||
*s_output_head, *s_output;
|
||||
uint16_t current_enqueued_cbs = 0;
|
||||
|
||||
uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs)
|
||||
& q->sw_ring_wrap_mask);
|
||||
desc = q->ring_addr + desc_idx;
|
||||
uint64_t fcw_offset = (desc_idx << 8) + ACC_DESC_FCW_OFFSET;
|
||||
acc200_fcw_td_fill(op, &desc->req.fcw_td);
|
||||
|
||||
input = op->turbo_dec.input.data;
|
||||
h_output_head = h_output = op->turbo_dec.hard_output.data;
|
||||
s_output_head = s_output = op->turbo_dec.soft_output.data;
|
||||
in_offset = op->turbo_dec.input.offset;
|
||||
h_out_offset = op->turbo_dec.hard_output.offset;
|
||||
s_out_offset = op->turbo_dec.soft_output.offset;
|
||||
h_out_length = s_out_length = 0;
|
||||
mbuf_total_left = op->turbo_dec.input.length;
|
||||
c = op->turbo_dec.tb_params.c;
|
||||
r = op->turbo_dec.tb_params.r;
|
||||
|
||||
while (mbuf_total_left > 0 && r < c) {
|
||||
|
||||
seg_total_left = rte_pktmbuf_data_len(input) - in_offset;
|
||||
|
||||
/* Set up DMA descriptor */
|
||||
desc = q->ring_addr + ((q->sw_ring_head + total_enqueued_cbs)
|
||||
& q->sw_ring_wrap_mask);
|
||||
desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset;
|
||||
desc->req.data_ptrs[0].blen = ACC_FCW_TD_BLEN;
|
||||
ret = acc200_dma_desc_td_fill(op, &desc->req, &input,
|
||||
h_output, s_output, &in_offset, &h_out_offset,
|
||||
&s_out_offset, &h_out_length, &s_out_length,
|
||||
&mbuf_total_left, &seg_total_left, r);
|
||||
|
||||
if (unlikely(ret < 0))
|
||||
return ret;
|
||||
|
||||
/* Hard output */
|
||||
mbuf_append(h_output_head, h_output, h_out_length);
|
||||
|
||||
/* Soft output */
|
||||
if (check_bit(op->turbo_dec.op_flags,
|
||||
RTE_BBDEV_TURBO_SOFT_OUTPUT))
|
||||
mbuf_append(s_output_head, s_output, s_out_length);
|
||||
|
||||
/* Set total number of CBs in TB */
|
||||
desc->req.cbs_in_tb = cbs_in_tb;
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
rte_memdump(stderr, "FCW", &desc->req.fcw_td,
|
||||
sizeof(desc->req.fcw_td) - 8);
|
||||
rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc));
|
||||
#endif
|
||||
|
||||
if (seg_total_left == 0) {
|
||||
/* Go to the next mbuf */
|
||||
input = input->next;
|
||||
in_offset = 0;
|
||||
h_output = h_output->next;
|
||||
h_out_offset = 0;
|
||||
|
||||
if (check_bit(op->turbo_dec.op_flags,
|
||||
RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
|
||||
s_output = s_output->next;
|
||||
s_out_offset = 0;
|
||||
}
|
||||
}
|
||||
|
||||
total_enqueued_cbs++;
|
||||
current_enqueued_cbs++;
|
||||
r++;
|
||||
}
|
||||
|
||||
/* Set SDone on last CB descriptor for TB mode */
|
||||
desc->req.sdone_enable = 1;
|
||||
desc->req.irq_enable = q->irq_enable;
|
||||
|
||||
return current_enqueued_cbs;
|
||||
}
|
||||
|
||||
/* Enqueue encode operations for ACC200 device in CB mode. */
|
||||
static uint16_t
|
||||
acc200_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_enc_op **ops, uint16_t num)
|
||||
{
|
||||
struct acc_queue *q = q_data->queue_private;
|
||||
int32_t avail = acc_ring_avail_enq(q);
|
||||
uint16_t i;
|
||||
union acc_dma_desc *desc;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < num; ++i) {
|
||||
/* Check if there are available space for further processing */
|
||||
if (unlikely(avail - 1 < 0)) {
|
||||
acc_enqueue_ring_full(q_data);
|
||||
break;
|
||||
}
|
||||
avail -= 1;
|
||||
|
||||
ret = enqueue_enc_one_op_cb(q, ops[i], i);
|
||||
if (ret < 0) {
|
||||
acc_enqueue_invalid(q_data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (unlikely(i == 0))
|
||||
return 0; /* Nothing to enqueue */
|
||||
|
||||
/* Set SDone in last CB in enqueued ops for CB mode*/
|
||||
desc = q->ring_addr + ((q->sw_ring_head + i - 1)
|
||||
& q->sw_ring_wrap_mask);
|
||||
desc->req.sdone_enable = 1;
|
||||
desc->req.irq_enable = q->irq_enable;
|
||||
|
||||
acc_dma_enqueue(q, i, &q_data->queue_stats);
|
||||
|
||||
/* Update stats */
|
||||
q_data->queue_stats.enqueued_count += i;
|
||||
q_data->queue_stats.enqueue_err_count += num - i;
|
||||
return i;
|
||||
}
|
||||
|
||||
/** Enqueue encode operations for ACC200 device in CB mode. */
|
||||
static inline uint16_t
|
||||
acc200_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data,
|
||||
@ -1443,6 +1968,45 @@ acc200_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data,
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Enqueue encode operations for ACC200 device in TB mode. */
|
||||
static uint16_t
|
||||
acc200_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_enc_op **ops, uint16_t num)
|
||||
{
|
||||
struct acc_queue *q = q_data->queue_private;
|
||||
int32_t avail = acc_ring_avail_enq(q);
|
||||
uint16_t i, enqueued_cbs = 0;
|
||||
uint8_t cbs_in_tb;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < num; ++i) {
|
||||
cbs_in_tb = get_num_cbs_in_tb_enc(&ops[i]->turbo_enc);
|
||||
/* Check if there are available space for further processing */
|
||||
if (unlikely((avail - cbs_in_tb < 0) || (cbs_in_tb == 0))) {
|
||||
acc_enqueue_ring_full(q_data);
|
||||
break;
|
||||
}
|
||||
avail -= cbs_in_tb;
|
||||
|
||||
ret = enqueue_enc_one_op_tb(q, ops[i], enqueued_cbs, cbs_in_tb);
|
||||
if (ret <= 0) {
|
||||
acc_enqueue_invalid(q_data);
|
||||
break;
|
||||
}
|
||||
enqueued_cbs += ret;
|
||||
}
|
||||
if (unlikely(enqueued_cbs == 0))
|
||||
return 0; /* Nothing to enqueue */
|
||||
|
||||
acc_dma_enqueue(q, enqueued_cbs, &q_data->queue_stats);
|
||||
|
||||
/* Update stats */
|
||||
q_data->queue_stats.enqueued_count += i;
|
||||
q_data->queue_stats.enqueue_err_count += num - i;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Enqueue LDPC encode operations for ACC200 device in TB mode. */
|
||||
static uint16_t
|
||||
acc200_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data,
|
||||
@ -1482,6 +2046,20 @@ acc200_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data,
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Enqueue encode operations for ACC200 device. */
|
||||
static uint16_t
|
||||
acc200_enqueue_enc(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_enc_op **ops, uint16_t num)
|
||||
{
|
||||
int32_t aq_avail = acc_aq_avail(q_data, num);
|
||||
if (unlikely((aq_avail <= 0) || (num == 0)))
|
||||
return 0;
|
||||
if (ops[0]->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
|
||||
return acc200_enqueue_enc_tb(q_data, ops, num);
|
||||
else
|
||||
return acc200_enqueue_enc_cb(q_data, ops, num);
|
||||
}
|
||||
|
||||
/* Enqueue encode operations for ACC200 device. */
|
||||
static uint16_t
|
||||
acc200_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
|
||||
@ -1496,6 +2074,47 @@ acc200_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
|
||||
return acc200_enqueue_ldpc_enc_cb(q_data, ops, num);
|
||||
}
|
||||
|
||||
|
||||
/* Enqueue decode operations for ACC200 device in CB mode. */
|
||||
static uint16_t
|
||||
acc200_enqueue_dec_cb(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_dec_op **ops, uint16_t num)
|
||||
{
|
||||
struct acc_queue *q = q_data->queue_private;
|
||||
int32_t avail = acc_ring_avail_enq(q);
|
||||
uint16_t i;
|
||||
union acc_dma_desc *desc;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < num; ++i) {
|
||||
/* Check if there are available space for further processing. */
|
||||
if (unlikely(avail - 1 < 0))
|
||||
break;
|
||||
avail -= 1;
|
||||
|
||||
ret = enqueue_dec_one_op_cb(q, ops[i], i);
|
||||
if (ret < 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (unlikely(i == 0))
|
||||
return 0; /* Nothing to enqueue. */
|
||||
|
||||
/* Set SDone in last CB in enqueued ops for CB mode. */
|
||||
desc = q->ring_addr + ((q->sw_ring_head + i - 1)
|
||||
& q->sw_ring_wrap_mask);
|
||||
desc->req.sdone_enable = 1;
|
||||
desc->req.irq_enable = q->irq_enable;
|
||||
|
||||
acc_dma_enqueue(q, i, &q_data->queue_stats);
|
||||
|
||||
/* Update stats. */
|
||||
q_data->queue_stats.enqueued_count += i;
|
||||
q_data->queue_stats.enqueue_err_count += num - i;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Enqueue decode operations for ACC200 device in TB mode. */
|
||||
static uint16_t
|
||||
acc200_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data,
|
||||
@ -1580,6 +2199,58 @@ acc200_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data,
|
||||
return i;
|
||||
}
|
||||
|
||||
|
||||
/* Enqueue decode operations for ACC200 device in TB mode */
|
||||
static uint16_t
|
||||
acc200_enqueue_dec_tb(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_dec_op **ops, uint16_t num)
|
||||
{
|
||||
struct acc_queue *q = q_data->queue_private;
|
||||
int32_t avail = acc_ring_avail_enq(q);
|
||||
uint16_t i, enqueued_cbs = 0;
|
||||
uint8_t cbs_in_tb;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < num; ++i) {
|
||||
cbs_in_tb = get_num_cbs_in_tb_dec(&ops[i]->turbo_dec);
|
||||
/* Check if there are available space for further processing */
|
||||
if (unlikely((avail - cbs_in_tb < 0) || (cbs_in_tb == 0))) {
|
||||
acc_enqueue_ring_full(q_data);
|
||||
break;
|
||||
}
|
||||
avail -= cbs_in_tb;
|
||||
|
||||
ret = enqueue_dec_one_op_tb(q, ops[i], enqueued_cbs, cbs_in_tb);
|
||||
if (ret <= 0) {
|
||||
acc_enqueue_invalid(q_data);
|
||||
break;
|
||||
}
|
||||
enqueued_cbs += ret;
|
||||
}
|
||||
|
||||
acc_dma_enqueue(q, enqueued_cbs, &q_data->queue_stats);
|
||||
|
||||
/* Update stats */
|
||||
q_data->queue_stats.enqueued_count += i;
|
||||
q_data->queue_stats.enqueue_err_count += num - i;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Enqueue decode operations for ACC200 device. */
|
||||
static uint16_t
|
||||
acc200_enqueue_dec(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_dec_op **ops, uint16_t num)
|
||||
{
|
||||
int32_t aq_avail = acc_aq_avail(q_data, num);
|
||||
if (unlikely((aq_avail <= 0) || (num == 0)))
|
||||
return 0;
|
||||
if (ops[0]->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
|
||||
return acc200_enqueue_dec_tb(q_data, ops, num);
|
||||
else
|
||||
return acc200_enqueue_dec_cb(q_data, ops, num);
|
||||
}
|
||||
|
||||
/* Enqueue decode operations for ACC200 device. */
|
||||
static uint16_t
|
||||
acc200_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
|
||||
@ -1712,6 +2383,57 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,
|
||||
return current_dequeued_descs;
|
||||
}
|
||||
|
||||
/* Dequeue one decode operation from ACC200 device in CB mode. */
|
||||
static inline int
|
||||
dequeue_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,
|
||||
struct acc_queue *q, struct rte_bbdev_dec_op **ref_op,
|
||||
uint16_t dequeued_cbs, uint32_t *aq_dequeued)
|
||||
{
|
||||
union acc_dma_desc *desc, atom_desc;
|
||||
union acc_dma_rsp_desc rsp;
|
||||
struct rte_bbdev_dec_op *op;
|
||||
|
||||
desc = q->ring_addr + ((q->sw_ring_tail + dequeued_cbs) & q->sw_ring_wrap_mask);
|
||||
atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED);
|
||||
|
||||
/* Check fdone bit. */
|
||||
if (!(atom_desc.rsp.val & ACC_FDONE))
|
||||
return -1;
|
||||
|
||||
rsp.val = atom_desc.rsp.val;
|
||||
rte_bbdev_log_debug("Resp. desc %p: %x\n", desc, rsp.val);
|
||||
|
||||
/* Dequeue. */
|
||||
op = desc->req.op_addr;
|
||||
|
||||
/* Clearing status, it will be set based on response. */
|
||||
op->status = 0;
|
||||
op->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);
|
||||
op->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);
|
||||
op->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);
|
||||
if (op->status != 0) {
|
||||
/* These errors are not expected. */
|
||||
q_data->queue_stats.dequeue_err_count++;
|
||||
}
|
||||
|
||||
/* CRC invalid if error exists. */
|
||||
if (!op->status)
|
||||
op->status |= rsp.crc_status << RTE_BBDEV_CRC_ERROR;
|
||||
op->turbo_dec.iter_count = (uint8_t) rsp.iter_cnt;
|
||||
/* Check if this is the last desc in batch (Atomic Queue). */
|
||||
if (desc->req.last_desc_in_batch) {
|
||||
(*aq_dequeued)++;
|
||||
desc->req.last_desc_in_batch = 0;
|
||||
}
|
||||
desc->rsp.val = ACC_DMA_DESC_TYPE;
|
||||
desc->rsp.add_info_0 = 0;
|
||||
desc->rsp.add_info_1 = 0;
|
||||
*ref_op = op;
|
||||
|
||||
/* One CB (op) was successfully dequeued. */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Dequeue one decode operations from ACC200 device in CB mode. */
|
||||
static inline int
|
||||
dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,
|
||||
@ -1853,6 +2575,48 @@ dequeue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op **ref_op,
|
||||
return cb_idx;
|
||||
}
|
||||
|
||||
/* Dequeue encode operations from ACC200 device. */
|
||||
static uint16_t
|
||||
acc200_dequeue_enc(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_enc_op **ops, uint16_t num)
|
||||
{
|
||||
struct acc_queue *q = q_data->queue_private;
|
||||
uint32_t avail = acc_ring_avail_deq(q);
|
||||
uint32_t aq_dequeued = 0;
|
||||
uint16_t i, dequeued_ops = 0, dequeued_descs = 0;
|
||||
int ret, cbm;
|
||||
struct rte_bbdev_enc_op *op;
|
||||
if (avail == 0)
|
||||
return 0;
|
||||
op = (q->ring_addr + (q->sw_ring_tail &
|
||||
q->sw_ring_wrap_mask))->req.op_addr;
|
||||
|
||||
cbm = op->turbo_enc.code_block_mode;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
if (cbm == RTE_BBDEV_TRANSPORT_BLOCK)
|
||||
ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops],
|
||||
&dequeued_ops, &aq_dequeued,
|
||||
&dequeued_descs);
|
||||
else
|
||||
ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops],
|
||||
&dequeued_ops, &aq_dequeued,
|
||||
&dequeued_descs);
|
||||
if (ret < 0)
|
||||
break;
|
||||
if (dequeued_ops >= num)
|
||||
break;
|
||||
}
|
||||
|
||||
q->aq_dequeued += aq_dequeued;
|
||||
q->sw_ring_tail += dequeued_descs;
|
||||
|
||||
/* Update enqueue stats */
|
||||
q_data->queue_stats.dequeued_count += dequeued_ops;
|
||||
|
||||
return dequeued_ops;
|
||||
}
|
||||
|
||||
/* Dequeue LDPC encode operations from ACC200 device. */
|
||||
static uint16_t
|
||||
acc200_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
|
||||
@ -1893,6 +2657,46 @@ acc200_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
|
||||
return dequeued_ops;
|
||||
}
|
||||
|
||||
/* Dequeue decode operations from ACC200 device. */
|
||||
static uint16_t
|
||||
acc200_dequeue_dec(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_dec_op **ops, uint16_t num)
|
||||
{
|
||||
struct acc_queue *q = q_data->queue_private;
|
||||
uint16_t dequeue_num;
|
||||
uint32_t avail = acc_ring_avail_deq(q);
|
||||
uint32_t aq_dequeued = 0;
|
||||
uint16_t i;
|
||||
uint16_t dequeued_cbs = 0;
|
||||
struct rte_bbdev_dec_op *op;
|
||||
int ret;
|
||||
|
||||
dequeue_num = (avail < num) ? avail : num;
|
||||
|
||||
for (i = 0; i < dequeue_num; ++i) {
|
||||
op = (q->ring_addr + ((q->sw_ring_tail + dequeued_cbs)
|
||||
& q->sw_ring_wrap_mask))->req.op_addr;
|
||||
if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
|
||||
ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs,
|
||||
&aq_dequeued);
|
||||
else
|
||||
ret = dequeue_dec_one_op_cb(q_data, q, &ops[i],
|
||||
dequeued_cbs, &aq_dequeued);
|
||||
|
||||
if (ret <= 0)
|
||||
break;
|
||||
dequeued_cbs += ret;
|
||||
}
|
||||
|
||||
q->aq_dequeued += aq_dequeued;
|
||||
q->sw_ring_tail += dequeued_cbs;
|
||||
|
||||
/* Update enqueue stats */
|
||||
q_data->queue_stats.dequeued_count += i;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Dequeue decode operations from ACC200 device. */
|
||||
static uint16_t
|
||||
acc200_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
|
||||
@ -1941,6 +2745,10 @@ acc200_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
|
||||
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
|
||||
|
||||
dev->dev_ops = &acc200_bbdev_ops;
|
||||
dev->enqueue_enc_ops = acc200_enqueue_enc;
|
||||
dev->enqueue_dec_ops = acc200_enqueue_dec;
|
||||
dev->dequeue_enc_ops = acc200_dequeue_enc;
|
||||
dev->dequeue_dec_ops = acc200_dequeue_dec;
|
||||
dev->enqueue_ldpc_enc_ops = acc200_enqueue_ldpc_enc;
|
||||
dev->enqueue_ldpc_dec_ops = acc200_enqueue_ldpc_dec;
|
||||
dev->dequeue_ldpc_enc_ops = acc200_dequeue_ldpc_enc;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user