d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

net/cxgbe: use I/O device memory read/write API

Browse Source 
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.

CC: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
This commit is contained in:
Santosh Shukla 2017-01-18 06:51:31 +05:30 committed by Thomas Monjalon
parent 7b0983c26c
commit c167acb612
3 changed files with 40 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/net/cxgbe/base/adapter.h
View File

@ -37,6 +37,7 @@
#define __T4_ADAPTER_H__ #define __T4_ADAPTER_H__
#include <rte_mbuf.h> #include <rte_mbuf.h>
#include <rte_io.h>
#include "cxgbe_compat.h" #include "cxgbe_compat.h"
#include "t4_regs_values.h" #include "t4_regs_values.h"
@ -324,7 +325,7 @@ struct adapter {
int use_unpacked_mode; /* unpacked rx mode state */ int use_unpacked_mode; /* unpacked rx mode state */
}; };
#define CXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg))) #define CXGBE_PCI_REG(reg) rte_read32(reg)
static inline uint64_t cxgbe_read_addr64(volatile void *addr) static inline uint64_t cxgbe_read_addr64(volatile void *addr)
{ {
@ -350,16 +351,21 @@ static inline uint32_t cxgbe_read_addr(volatile void *addr)
#define CXGBE_READ_REG64(adap, reg) \ #define CXGBE_READ_REG64(adap, reg) \
cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg))) cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
#define CXGBE_PCI_REG_WRITE(reg, value) ({ \ #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
CXGBE_PCI_REG((reg)) = (value); })
#define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
rte_write32_relaxed((value), (reg))
#define CXGBE_WRITE_REG(adap, reg, value) \ #define CXGBE_WRITE_REG(adap, reg, value) \
CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value)) CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
#define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val) static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
{ {
CXGBE_PCI_REG(addr) = val; CXGBE_PCI_REG_WRITE(addr, val);
CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4)) = (val >> 32); CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
return val; return val;
} }
@ -383,7 +389,7 @@ static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
} }
/** /**
* t4_write_reg - write a HW register * t4_write_reg - write a HW register with barrier
* @adapter: the adapter * @adapter: the adapter
* @reg_addr: the register address * @reg_addr: the register address
* @val: the value to write * @val: the value to write
@ -397,6 +403,22 @@ static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
CXGBE_WRITE_REG(adapter, reg_addr, val); CXGBE_WRITE_REG(adapter, reg_addr, val);
} }
/**
* t4_write_reg_relaxed - write a HW register with no barrier
* @adapter: the adapter
* @reg_addr: the register address
* @val: the value to write
*
* Write a 32-bit value into the given HW register.
*/
static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
u32 val)
{
CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
val);
CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
}
/** /**
* t4_read_reg64 - read a 64-bit HW register * t4_read_reg64 - read a 64-bit HW register
* @adapter: the adapter * @adapter: the adapter

8
drivers/net/cxgbe/cxgbe_compat.h
View File

@ -45,6 +45,7 @@
#include <rte_cycles.h> #include <rte_cycles.h>
#include <rte_spinlock.h> #include <rte_spinlock.h>
#include <rte_log.h> #include <rte_log.h>
#include <rte_io.h>
#define dev_printf(level, fmt, args...) \ #define dev_printf(level, fmt, args...) \
RTE_LOG(level, PMD, "rte_cxgbe_pmd: " fmt, ## args) RTE_LOG(level, PMD, "rte_cxgbe_pmd: " fmt, ## args)
@ -254,7 +255,7 @@ static inline unsigned long ilog2(unsigned long n)
static inline void writel(unsigned int val, volatile void __iomem *addr) static inline void writel(unsigned int val, volatile void __iomem *addr)
{ {
*(volatile unsigned int *)addr = val; rte_write32(val, addr);
} }
static inline void writeq(u64 val, volatile void __iomem *addr) static inline void writeq(u64 val, volatile void __iomem *addr)
@ -263,4 +264,9 @@ static inline void writeq(u64 val, volatile void __iomem *addr)
writel(val >> 32, (void *)((uintptr_t)addr + 4)); writel(val >> 32, (void *)((uintptr_t)addr + 4));
} }
static inline void writel_relaxed(unsigned int val, volatile void __iomem *addr)
{
rte_write32_relaxed(val, addr);
}
#endif /* _CXGBE_COMPAT_H_ */ #endif /* _CXGBE_COMPAT_H_ */

4
drivers/net/cxgbe/sge.c
View File

@ -338,10 +338,10 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
* mechanism. * mechanism.
*/ */
if (unlikely(!q->bar2_addr)) { if (unlikely(!q->bar2_addr)) {
t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL), t4_write_reg_relaxed(adap, MYPF_REG(A_SGE_PF_KDOORBELL),
val | V_QID(q->cntxt_id)); val | V_QID(q->cntxt_id));
} else { } else {
writel(val | V_QID(q->bar2_qid), writel_relaxed(val | V_QID(q->bar2_qid),
(void *)((uintptr_t)q->bar2_addr + (void *)((uintptr_t)q->bar2_addr +
SGE_UDB_KDOORBELL)); SGE_UDB_KDOORBELL));