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ixgbe/base: add new mac-dependent values for X540 and X550

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Add new values that vary by MAC type that are introduced in
x540, x550.
And remove some meaningless comments BTW.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
This commit is contained in:
Wenzhuo Lu 2015-06-24 11:26:17 +08:00 committed by Thomas Monjalon
parent 201c9139e5
commit c20290b383
1 changed files with 59 additions and 13 deletions
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72
drivers/net/ixgbe/base/ixgbe_type.h
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@ -165,18 +165,40 @@ POSSIBILITY OF SUCH DAMAGE.
#define IXGBE_EXVET 0x05078
/* NVM Registers */
#define IXGBE_EEC 0x10010
#define IXGBE_EERD 0x10014
#define IXGBE_EEWR 0x10018
#define IXGBE_FLA 0x1001C
#define IXGBE_EEC 0x10010
#define IXGBE_EEC_X540 IXGBE_EEC
#define IXGBE_EEC_X550 IXGBE_EEC
#define IXGBE_EEC_X550EM_x IXGBE_EEC
#define IXGBE_EEC_BY_MAC(_hw) IXGBE_EEC
#define IXGBE_EERD 0x10014
#define IXGBE_EEWR 0x10018
#define IXGBE_FLA 0x1001C
#define IXGBE_FLA_X540 IXGBE_FLA
#define IXGBE_FLA_X550 IXGBE_FLA
#define IXGBE_FLA_X550EM_x IXGBE_FLA
#define IXGBE_FLA_BY_MAC(_hw) IXGBE_FLA
#define IXGBE_EEMNGCTL 0x10110
#define IXGBE_EEMNGDATA 0x10114
#define IXGBE_FLMNGCTL 0x10118
#define IXGBE_FLMNGDATA 0x1011C
#define IXGBE_FLMNGCNT 0x10120
#define IXGBE_FLOP 0x1013C
#define IXGBE_GRC 0x10200
#define IXGBE_SRAMREL 0x10210
#define IXGBE_GRC 0x10200
#define IXGBE_GRC_X540 IXGBE_GRC
#define IXGBE_GRC_X550 IXGBE_GRC
#define IXGBE_GRC_X550EM_x IXGBE_GRC
#define IXGBE_GRC_BY_MAC(_hw) IXGBE_GRC
#define IXGBE_SRAMREL 0x10210
#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL
#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL
#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL
#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_SRAMREL
#define IXGBE_PHYDBG 0x10218
/* General Receive Control */
@ -1037,14 +1059,34 @@ struct ixgbe_dmac_config {
#define IXGBE_GSCN_2 0x11028
#define IXGBE_GSCN_3 0x1102C
#define IXGBE_FACTPS 0x10150
#define IXGBE_FACTPS_X540 IXGBE_FACTPS
#define IXGBE_FACTPS_X550 IXGBE_FACTPS
#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS
#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_FACTPS
#define IXGBE_PCIEANACTL 0x11040
#define IXGBE_SWSM 0x10140
#define IXGBE_SWSM_X540 IXGBE_SWSM
#define IXGBE_SWSM_X550 IXGBE_SWSM
#define IXGBE_SWSM_X550EM_x IXGBE_SWSM
#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_SWSM
#define IXGBE_FWSM 0x10148
#define IXGBE_FWSM_X540 IXGBE_FWSM
#define IXGBE_FWSM_X550 IXGBE_FWSM
#define IXGBE_FWSM_X550EM_x IXGBE_FWSM
#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_FWSM
#define IXGBE_SWFW_SYNC IXGBE_GSSR
#define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC
#define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC
#define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC
#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_SWFW_SYNC
#define IXGBE_GSSR 0x10160
#define IXGBE_MREVID 0x11064
#define IXGBE_DCA_ID 0x11070
#define IXGBE_DCA_CTRL 0x11074
#define IXGBE_SWFW_SYNC IXGBE_GSSR
/* PCI-E registers 82599-Specific */
#define IXGBE_GCR_EXT 0x11050
@ -3290,7 +3332,16 @@ union ixgbe_atr_hash_dword {
__be32 dword;
};
#define IXGBE_MVALS_INIT(m) \
#define IXGBE_MVALS_INIT(m) \
IXGBE_CAT(EEC, m), \
IXGBE_CAT(FLA, m), \
IXGBE_CAT(GRC, m), \
IXGBE_CAT(SRAMREL, m), \
IXGBE_CAT(FACTPS, m), \
IXGBE_CAT(SWSM, m), \
IXGBE_CAT(SWFW_SYNC, m), \
IXGBE_CAT(FWSM, m), \
IXGBE_CAT(SDP0_GPIEN, m), \
IXGBE_CAT(SDP1_GPIEN, m), \
IXGBE_CAT(SDP2_GPIEN, m), \
@ -3338,11 +3389,6 @@ enum ixgbe_mac_type {
ixgbe_mac_82599_vf,
ixgbe_mac_X540,
ixgbe_mac_X540_vf,
/*
* X550EM MAC type decoder:
* ixgbe_mac_X550EM_x: "x" = Xeon
* ixgbe_mac_X550EM_a: "a" = Atom
*/
ixgbe_mac_X550,
ixgbe_mac_X550EM_x,
ixgbe_mac_X550_vf,