igb: enable Rx queue interrupts for PF
The patch does below for igb PF: - Setup NIC to generate MSI-X interrupts - Set the IVAR register to map interrupt causes to vectors - Implement interrupt enable/disable functions Signed-off-by: Danny Zhou <danny.zhou@intel.com> Signed-off-by: Cunming Liang <cunming.liang@intel.com>
This commit is contained in:
Cunming Liang
Thomas Monjalon
parent
0eb609239e
commit
c3cd3de0ab
@ -105,6 +105,9 @@ static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
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static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
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#ifdef RTE_NEXT_ABI
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static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
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#endif
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static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
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static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
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static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
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@ -218,7 +221,6 @@ static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
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struct rte_dev_eeprom_info *eeprom);
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static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
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struct rte_dev_eeprom_info *eeprom);
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static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
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struct ether_addr *mc_addr_set,
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uint32_t nb_mc_addr);
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@ -229,6 +231,17 @@ static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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uint32_t flags);
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static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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#ifdef RTE_NEXT_ABI
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static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
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uint16_t queue_id);
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static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
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uint16_t queue_id);
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static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
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uint8_t queue, uint8_t msix_vector);
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static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
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uint8_t index, uint8_t offset);
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#endif
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static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
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/*
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* Define VF Stats MACRO for Non "cleared on read" register
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@ -289,6 +302,10 @@ static const struct eth_dev_ops eth_igb_ops = {
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.vlan_tpid_set = eth_igb_vlan_tpid_set,
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.vlan_offload_set = eth_igb_vlan_offload_set,
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.rx_queue_setup = eth_igb_rx_queue_setup,
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#ifdef RTE_NEXT_ABI
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.rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
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.rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
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#endif
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.rx_queue_release = eth_igb_rx_queue_release,
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.rx_queue_count = eth_igb_rx_queue_count,
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.rx_descriptor_done = eth_igb_rx_descriptor_done,
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@ -639,12 +656,6 @@ eth_igb_dev_init(struct rte_eth_dev *eth_dev)
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eth_dev->data->port_id, pci_dev->id.vendor_id,
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pci_dev->id.device_id);
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rte_intr_callback_register(&(pci_dev->intr_handle),
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eth_igb_interrupt_handler, (void *)eth_dev);
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/* enable uio intr after callback register */
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rte_intr_enable(&(pci_dev->intr_handle));
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/* enable support intr */
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igb_intr_enable(eth_dev);
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@ -879,7 +890,11 @@ eth_igb_start(struct rte_eth_dev *dev)
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct e1000_adapter *adapter =
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E1000_DEV_PRIVATE(dev->data->dev_private);
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int ret, i, mask;
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struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
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int ret, mask;
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#ifdef RTE_NEXT_ABI
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uint32_t intr_vector = 0;
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#endif
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uint32_t ctrl_ext;
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PMD_INIT_FUNC_TRACE();
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@ -920,6 +935,29 @@ eth_igb_start(struct rte_eth_dev *dev)
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/* configure PF module if SRIOV enabled */
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igb_pf_host_configure(dev);
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#ifdef RTE_NEXT_ABI
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/* check and configure queue intr-vector mapping */
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if (dev->data->dev_conf.intr_conf.rxq != 0)
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intr_vector = dev->data->nb_rx_queues;
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if (rte_intr_efd_enable(intr_handle, intr_vector))
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return -1;
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if (rte_intr_dp_is_en(intr_handle)) {
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intr_handle->intr_vec =
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rte_zmalloc("intr_vec",
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dev->data->nb_rx_queues * sizeof(int), 0);
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if (intr_handle->intr_vec == NULL) {
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PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
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" intr_vec\n", dev->data->nb_rx_queues);
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return -ENOMEM;
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}
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}
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#endif
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/* confiugre msix for rx interrupt */
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eth_igb_configure_msix_intr(dev);
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/* Configure for OS presence */
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igb_init_manageability(hw);
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@ -947,33 +985,9 @@ eth_igb_start(struct rte_eth_dev *dev)
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igb_vmdq_vlan_hw_filter_enable(dev);
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}
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/*
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* Configure the Interrupt Moderation register (EITR) with the maximum
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* possible value (0xFFFF) to minimize "System Partial Write" issued by
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* spurious [DMA] memory updates of RX and TX ring descriptors.
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*
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* With a EITR granularity of 2 microseconds in the 82576, only 7/8
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* spurious memory updates per second should be expected.
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* ((65535 * 2) / 1000.1000 ~= 0.131 second).
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*
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* Because interrupts are not used at all, the MSI-X is not activated
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* and interrupt moderation is controlled by EITR[0].
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*
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* Note that having [almost] disabled memory updates of RX and TX ring
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* descriptors through the Interrupt Moderation mechanism, memory
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* updates of ring descriptors are now moderated by the configurable
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* value of Write-Back Threshold registers.
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*/
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if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
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(hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
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(hw->mac.type == e1000_i211)) {
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uint32_t ivar;
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/* Enable all RX & TX queues in the IVAR registers */
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ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
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for (i = 0; i < 8; i++)
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E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
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/* Configure EITR with the maximum possible value (0xFFFF) */
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E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
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}
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@ -1024,8 +1038,25 @@ eth_igb_start(struct rte_eth_dev *dev)
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e1000_setup_link(hw);
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/* check if lsc interrupt feature is enabled */
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if (dev->data->dev_conf.intr_conf.lsc != 0)
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ret = eth_igb_lsc_interrupt_setup(dev);
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if (dev->data->dev_conf.intr_conf.lsc != 0) {
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if (rte_intr_allow_others(intr_handle)) {
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rte_intr_callback_register(intr_handle,
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eth_igb_interrupt_handler,
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(void *)dev);
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eth_igb_lsc_interrupt_setup(dev);
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} else
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PMD_INIT_LOG(INFO, "lsc won't enable because of"
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" no intr multiplex\n");
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}
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#ifdef RTE_NEXT_ABI
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/* check if rxq interrupt is enabled */
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if (dev->data->dev_conf.intr_conf.rxq != 0)
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eth_igb_rxq_interrupt_setup(dev);
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#endif
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/* enable uio/vfio intr/eventfd mapping */
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rte_intr_enable(intr_handle);
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/* resume enabled intr since hw reset */
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igb_intr_enable(dev);
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@ -1058,8 +1089,13 @@ eth_igb_stop(struct rte_eth_dev *dev)
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struct e1000_flex_filter *p_flex;
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struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
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struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
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struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
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igb_intr_disable(hw);
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/* disable intr eventfd mapping */
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rte_intr_disable(intr_handle);
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igb_pf_reset_hw(hw);
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E1000_WRITE_REG(hw, E1000_WUC, 0);
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@ -1108,6 +1144,15 @@ eth_igb_stop(struct rte_eth_dev *dev)
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rte_free(p_2tuple);
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}
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filter_info->twotuple_mask = 0;
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#ifdef RTE_NEXT_ABI
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/* Clean datapath event and queue/vec mapping */
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rte_intr_efd_disable(intr_handle);
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if (intr_handle->intr_vec != NULL) {
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rte_free(intr_handle->intr_vec);
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intr_handle->intr_vec = NULL;
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}
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#endif
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}
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static void
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@ -1117,6 +1162,9 @@ eth_igb_close(struct rte_eth_dev *dev)
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struct e1000_adapter *adapter =
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E1000_DEV_PRIVATE(dev->data->dev_private);
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struct rte_eth_link link;
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#ifdef RTE_NEXT_ABI
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struct rte_pci_device *pci_dev;
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#endif
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eth_igb_stop(dev);
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adapter->stopped = 1;
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@ -1136,6 +1184,14 @@ eth_igb_close(struct rte_eth_dev *dev)
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igb_dev_free_queues(dev);
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#ifdef RTE_NEXT_ABI
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pci_dev = dev->pci_dev;
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if (pci_dev->intr_handle.intr_vec) {
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rte_free(pci_dev->intr_handle.intr_vec);
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pci_dev->intr_handle.intr_vec = NULL;
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}
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#endif
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memset(&link, 0, sizeof(link));
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rte_igb_dev_atomic_write_link_status(dev, &link);
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}
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@ -1960,6 +2016,35 @@ eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
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return 0;
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}
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#ifdef RTE_NEXT_ABI
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/* It clears the interrupt causes and enables the interrupt.
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* It will be called once only during nic initialized.
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*
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* @param dev
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* Pointer to struct rte_eth_dev.
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*
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* @return
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* - On success, zero.
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* - On failure, a negative value.
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*/
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static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
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{
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uint32_t mask, regval;
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct rte_eth_dev_info dev_info;
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memset(&dev_info, 0, sizeof(dev_info));
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eth_igb_infos_get(dev, &dev_info);
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mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
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regval = E1000_READ_REG(hw, E1000_EIMS);
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E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
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return 0;
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}
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#endif
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/*
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* It reads ICR and gets interrupt causes, check it and set a bit flag
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* to update link status.
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@ -4051,5 +4136,163 @@ static struct rte_driver pmd_igbvf_drv = {
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.init = rte_igbvf_pmd_init,
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};
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#ifdef RTE_NEXT_ABI
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static int
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eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
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{
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t mask = 1 << queue_id;
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E1000_WRITE_REG(hw, E1000_EIMC, mask);
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E1000_WRITE_FLUSH(hw);
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return 0;
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}
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static int
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eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
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{
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t mask = 1 << queue_id;
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uint32_t regval;
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regval = E1000_READ_REG(hw, E1000_EIMS);
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E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
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E1000_WRITE_FLUSH(hw);
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rte_intr_enable(&dev->pci_dev->intr_handle);
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return 0;
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}
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static void
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eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
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uint8_t index, uint8_t offset)
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{
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uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
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/* clear bits */
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val &= ~((uint32_t)0xFF << offset);
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/* write vector and valid bit */
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val |= (msix_vector | E1000_IVAR_VALID) << offset;
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E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
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}
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static void
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eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
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uint8_t queue, uint8_t msix_vector)
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{
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uint32_t tmp = 0;
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if (hw->mac.type == e1000_82575) {
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if (direction == 0)
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tmp = E1000_EICR_RX_QUEUE0 << queue;
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else if (direction == 1)
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tmp = E1000_EICR_TX_QUEUE0 << queue;
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E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
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} else if (hw->mac.type == e1000_82576) {
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if ((direction == 0) || (direction == 1))
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eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
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((queue & 0x8) << 1) +
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8 * direction);
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} else if ((hw->mac.type == e1000_82580) ||
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(hw->mac.type == e1000_i350) ||
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(hw->mac.type == e1000_i354) ||
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(hw->mac.type == e1000_i210) ||
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(hw->mac.type == e1000_i211)) {
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if ((direction == 0) || (direction == 1))
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eth_igb_write_ivar(hw, msix_vector,
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queue >> 1,
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((queue & 0x1) << 4) +
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8 * direction);
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}
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}
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#endif
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/* Sets up the hardware to generate MSI-X interrupts properly
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* @hw
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* board private structure
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*/
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static void
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eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
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{
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#ifdef RTE_NEXT_ABI
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int queue_id;
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uint32_t tmpval, regval, intr_mask;
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t vec = 0;
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#endif
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struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
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/* won't configure msix register if no mapping is done
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* between intr vector and event fd
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*/
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if (!rte_intr_dp_is_en(intr_handle))
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return;
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#ifdef RTE_NEXT_ABI
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/* set interrupt vector for other causes */
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if (hw->mac.type == e1000_82575) {
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tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
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/* enable MSI-X PBA support */
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tmpval |= E1000_CTRL_EXT_PBA_CLR;
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/* Auto-Mask interrupts upon ICR read */
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tmpval |= E1000_CTRL_EXT_EIAME;
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tmpval |= E1000_CTRL_EXT_IRCA;
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E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
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/* enable msix_other interrupt */
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E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
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regval = E1000_READ_REG(hw, E1000_EIAC);
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E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
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regval = E1000_READ_REG(hw, E1000_EIAM);
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E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
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} else if ((hw->mac.type == e1000_82576) ||
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(hw->mac.type == e1000_82580) ||
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(hw->mac.type == e1000_i350) ||
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(hw->mac.type == e1000_i354) ||
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(hw->mac.type == e1000_i210) ||
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(hw->mac.type == e1000_i211)) {
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/* turn on MSI-X capability first */
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E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
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E1000_GPIE_PBA | E1000_GPIE_EIAME |
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E1000_GPIE_NSICR);
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intr_mask = (1 << intr_handle->max_intr) - 1;
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regval = E1000_READ_REG(hw, E1000_EIAC);
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E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
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/* enable msix_other interrupt */
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regval = E1000_READ_REG(hw, E1000_EIMS);
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E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
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tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
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E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
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}
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/* use EIAM to auto-mask when MSI-X interrupt
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* is asserted, this saves a register write for every interrupt
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*/
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intr_mask = (1 << intr_handle->nb_efd) - 1;
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regval = E1000_READ_REG(hw, E1000_EIAM);
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E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
|
||||
|
||||
for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
|
||||
eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
|
||||
intr_handle->intr_vec[queue_id] = vec;
|
||||
if (vec < intr_handle->nb_efd - 1)
|
||||
vec++;
|
||||
}
|
||||
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
#endif
|
||||
}
|
||||
|
||||
PMD_REGISTER_DRIVER(pmd_igb_drv);
|
||||
PMD_REGISTER_DRIVER(pmd_igbvf_drv);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user