net/octeontx2: support TM debug
Add debug support to TM to dump configured topology and registers. Also enable debug dump when sq flush fails. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
This commit is contained in:
Nithin Dabilpuram
Ferruh Yigit
parent
89d08a1ff8
commit
c3f733efd4
@ -464,6 +464,7 @@ int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
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struct rte_dev_reg_info *regs);
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int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
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void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
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void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
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/* Stats */
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int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
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@ -6,6 +6,7 @@
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#define nix_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
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#define NIX_REG_INFO(reg) {reg, #reg}
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#define NIX_REG_NAME_SZ 48
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struct nix_lf_reg_info {
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uint32_t offset;
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@ -390,9 +391,14 @@ otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev)
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int rc, q, rq = eth_dev->data->nb_rx_queues;
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int sq = eth_dev->data->nb_tx_queues;
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struct otx2_mbox *mbox = dev->mbox;
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struct npa_aq_enq_rsp *npa_rsp;
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struct npa_aq_enq_req *npa_aq;
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struct otx2_npa_lf *npa_lf;
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struct nix_aq_enq_rsp *rsp;
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struct nix_aq_enq_req *aq;
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npa_lf = otx2_npa_lf_obj_get();
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for (q = 0; q < rq; q++) {
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aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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aq->qidx = q;
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@ -438,6 +444,36 @@ otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev)
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nix_dump("============== port=%d sq=%d ===============",
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eth_dev->data->port_id, q);
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nix_lf_sq_dump(&rsp->sq);
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if (!npa_lf) {
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otx2_err("NPA LF doesn't exist");
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continue;
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}
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/* Dump SQB Aura minimal info */
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npa_aq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
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npa_aq->aura_id = rsp->sq.sqb_aura;
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npa_aq->ctype = NPA_AQ_CTYPE_AURA;
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npa_aq->op = NPA_AQ_INSTOP_READ;
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rc = otx2_mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);
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if (rc) {
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otx2_err("Failed to get sq's sqb_aura context");
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continue;
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}
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nix_dump("\nSQB Aura W0: Pool addr\t\t0x%"PRIx64"",
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npa_rsp->aura.pool_addr);
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nix_dump("SQB Aura W1: ena\t\t\t%d",
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npa_rsp->aura.ena);
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nix_dump("SQB Aura W2: count\t\t%"PRIx64"",
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(uint64_t)npa_rsp->aura.count);
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nix_dump("SQB Aura W3: limit\t\t%"PRIx64"",
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(uint64_t)npa_rsp->aura.limit);
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nix_dump("SQB Aura W3: fc_ena\t\t%d",
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npa_rsp->aura.fc_ena);
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nix_dump("SQB Aura W4: fc_addr\t\t0x%"PRIx64"\n",
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npa_rsp->aura.fc_addr);
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}
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fail:
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@ -498,3 +534,278 @@ otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)
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nix_dump("W5: vtag0_ptr \t%d\t\tvtag1_ptr \t%d\t\tflow_key_alg \t%d",
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rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);
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}
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static uint8_t
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prepare_nix_tm_reg_dump(uint16_t hw_lvl, uint16_t schq, uint16_t link,
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uint64_t *reg, char regstr[][NIX_REG_NAME_SZ])
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{
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uint8_t k = 0;
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switch (hw_lvl) {
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case NIX_TXSCH_LVL_SMQ:
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reg[k] = NIX_AF_SMQX_CFG(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_SMQ[%u]_CFG", schq);
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reg[k] = NIX_AF_MDQX_PARENT(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_MDQ[%u]_PARENT", schq);
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reg[k] = NIX_AF_MDQX_SCHEDULE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_MDQ[%u]_SCHEDULE", schq);
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reg[k] = NIX_AF_MDQX_PIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_MDQ[%u]_PIR", schq);
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reg[k] = NIX_AF_MDQX_CIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_MDQ[%u]_CIR", schq);
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reg[k] = NIX_AF_MDQX_SHAPE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_MDQ[%u]_SHAPE", schq);
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reg[k] = NIX_AF_MDQX_SW_XOFF(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_MDQ[%u]_SW_XOFF", schq);
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break;
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case NIX_TXSCH_LVL_TL4:
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reg[k] = NIX_AF_TL4X_PARENT(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL4[%u]_PARENT", schq);
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reg[k] = NIX_AF_TL4X_TOPOLOGY(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL4[%u]_TOPOLOGY", schq);
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reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL4[%u]_SDP_LINK_CFG", schq);
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reg[k] = NIX_AF_TL4X_SCHEDULE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL4[%u]_SCHEDULE", schq);
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reg[k] = NIX_AF_TL4X_PIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL4[%u]_PIR", schq);
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reg[k] = NIX_AF_TL4X_CIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL4[%u]_CIR", schq);
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reg[k] = NIX_AF_TL4X_SHAPE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL4[%u]_SHAPE", schq);
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reg[k] = NIX_AF_TL4X_SW_XOFF(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL4[%u]_SW_XOFF", schq);
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break;
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case NIX_TXSCH_LVL_TL3:
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reg[k] = NIX_AF_TL3X_PARENT(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3[%u]_PARENT", schq);
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reg[k] = NIX_AF_TL3X_TOPOLOGY(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3[%u]_TOPOLOGY", schq);
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reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
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reg[k] = NIX_AF_TL3X_SCHEDULE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3[%u]_SCHEDULE", schq);
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reg[k] = NIX_AF_TL3X_PIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3[%u]_PIR", schq);
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reg[k] = NIX_AF_TL3X_CIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3[%u]_CIR", schq);
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reg[k] = NIX_AF_TL3X_SHAPE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3[%u]_SHAPE", schq);
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reg[k] = NIX_AF_TL3X_SW_XOFF(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3[%u]_SW_XOFF", schq);
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break;
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case NIX_TXSCH_LVL_TL2:
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reg[k] = NIX_AF_TL2X_PARENT(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL2[%u]_PARENT", schq);
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reg[k] = NIX_AF_TL2X_TOPOLOGY(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL2[%u]_TOPOLOGY", schq);
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reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
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reg[k] = NIX_AF_TL2X_SCHEDULE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL2[%u]_SCHEDULE", schq);
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reg[k] = NIX_AF_TL2X_PIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL2[%u]_PIR", schq);
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reg[k] = NIX_AF_TL2X_CIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL2[%u]_CIR", schq);
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reg[k] = NIX_AF_TL2X_SHAPE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL2[%u]_SHAPE", schq);
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reg[k] = NIX_AF_TL2X_SW_XOFF(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL2[%u]_SW_XOFF", schq);
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break;
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case NIX_TXSCH_LVL_TL1:
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reg[k] = NIX_AF_TL1X_TOPOLOGY(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL1[%u]_TOPOLOGY", schq);
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reg[k] = NIX_AF_TL1X_SCHEDULE(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL1[%u]_SCHEDULE", schq);
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reg[k] = NIX_AF_TL1X_CIR(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL1[%u]_CIR", schq);
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reg[k] = NIX_AF_TL1X_SW_XOFF(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL1[%u]_SW_XOFF", schq);
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reg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);
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snprintf(regstr[k++], NIX_REG_NAME_SZ,
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"NIX_AF_TL1[%u]_DROPPED_PACKETS", schq);
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break;
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default:
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break;
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}
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if (k > MAX_REGS_PER_MBOX_MSG) {
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nix_dump("\t!!!NIX TM Registers request overflow!!!");
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return 0;
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}
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return k;
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}
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/* Dump TM hierarchy and registers */
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void
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otx2_nix_tm_dump(struct otx2_eth_dev *dev)
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{
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char regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];
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struct otx2_nix_tm_node *tm_node, *root_node, *parent;
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uint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];
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struct nix_txschq_config *req;
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const char *lvlstr, *parent_lvlstr;
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struct nix_txschq_config *rsp;
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uint32_t schq, parent_schq;
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int hw_lvl, j, k, rc;
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nix_dump("===TM hierarchy and registers dump of %s===",
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dev->eth_dev->data->name);
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root_node = NULL;
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for (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++) {
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TAILQ_FOREACH(tm_node, &dev->node_list, node) {
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if (tm_node->hw_lvl != hw_lvl)
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continue;
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parent = tm_node->parent;
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if (hw_lvl == NIX_TXSCH_LVL_CNT) {
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lvlstr = "SQ";
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schq = tm_node->id;
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} else {
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lvlstr = nix_hwlvl2str(tm_node->hw_lvl);
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schq = tm_node->hw_id;
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}
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if (parent) {
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parent_schq = parent->hw_id;
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parent_lvlstr =
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nix_hwlvl2str(parent->hw_lvl);
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} else if (tm_node->hw_lvl == NIX_TXSCH_LVL_TL1) {
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parent_schq = otx2_nix_get_link(dev);
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parent_lvlstr = "LINK";
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} else {
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parent_schq = tm_node->parent_hw_id;
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parent_lvlstr =
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nix_hwlvl2str(tm_node->hw_lvl + 1);
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}
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nix_dump("%s_%d->%s_%d", lvlstr, schq,
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parent_lvlstr, parent_schq);
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if (!(tm_node->flags & NIX_TM_NODE_HWRES))
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continue;
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/* Need to dump TL1 when root is TL2 */
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if (tm_node->hw_lvl == dev->otx2_tm_root_lvl)
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root_node = tm_node;
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/* Dump registers only when HWRES is present */
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k = prepare_nix_tm_reg_dump(tm_node->hw_lvl, schq,
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otx2_nix_get_link(dev), reg,
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regstr);
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if (!k)
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continue;
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req = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);
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req->read = 1;
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req->lvl = tm_node->hw_lvl;
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req->num_regs = k;
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otx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
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rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
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if (!rc) {
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for (j = 0; j < k; j++)
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nix_dump("\t%s=0x%016"PRIx64,
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regstr[j], rsp->regval[j]);
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} else {
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nix_dump("\t!!!Failed to dump registers!!!");
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}
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}
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nix_dump("\n");
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}
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/* Dump TL1 node data when root level is TL2 */
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if (root_node && root_node->hw_lvl == NIX_TXSCH_LVL_TL2) {
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k = prepare_nix_tm_reg_dump(NIX_TXSCH_LVL_TL1,
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root_node->parent_hw_id,
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otx2_nix_get_link(dev),
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reg, regstr);
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if (!k)
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return;
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req = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);
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req->read = 1;
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req->lvl = NIX_TXSCH_LVL_TL1;
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req->num_regs = k;
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otx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
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rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
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if (!rc) {
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for (j = 0; j < k; j++)
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nix_dump("\t%s=0x%016"PRIx64,
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regstr[j], rsp->regval[j]);
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} else {
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nix_dump("\t!!!Failed to dump registers!!!");
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}
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}
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otx2_nix_queues_ctx_dump(dev->eth_dev);
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}
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@ -28,8 +28,8 @@ uint64_t shaper2regval(struct shaper_params *shaper)
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(shaper->mantissa << 1);
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}
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static int
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nix_get_link(struct otx2_eth_dev *dev)
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int
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otx2_nix_get_link(struct otx2_eth_dev *dev)
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{
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int link = 13 /* SDP */;
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uint16_t lmac_chan;
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@ -574,7 +574,7 @@ populate_tm_reg(struct otx2_eth_dev *dev,
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if (!otx2_dev_is_sdp(dev) &&
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dev->link_cfg_lvl == NIX_TXSCH_LVL_TL3) {
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reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,
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nix_get_link(dev));
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otx2_nix_get_link(dev));
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regval[k] = BIT_ULL(12) | nix_get_relchan(dev);
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k++;
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}
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@ -594,7 +594,7 @@ populate_tm_reg(struct otx2_eth_dev *dev,
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if (!otx2_dev_is_sdp(dev) &&
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dev->link_cfg_lvl == NIX_TXSCH_LVL_TL2) {
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reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,
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nix_get_link(dev));
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otx2_nix_get_link(dev));
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||||
regval[k] = BIT_ULL(12) | nix_get_relchan(dev);
|
||||
k++;
|
||||
}
|
||||
@ -990,6 +990,7 @@ nix_txq_flush_sq_spin(struct otx2_eth_txq *txq)
|
||||
|
||||
return 0;
|
||||
exit:
|
||||
otx2_nix_tm_dump(dev);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
|
||||
@ -23,6 +23,7 @@ int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,
|
||||
int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);
|
||||
int otx2_nix_sq_flush_post(void *_txq);
|
||||
int otx2_nix_sq_enable(void *_txq);
|
||||
int otx2_nix_get_link(struct otx2_eth_dev *dev);
|
||||
int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);
|
||||
|
||||
struct otx2_nix_tm_node {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user